1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2002-2010 4 * Copyright 2020 NXP 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 */ 7 8 #ifndef __ASM_GBL_DATA_H 9 #define __ASM_GBL_DATA_H 10 11 #include "config.h" 12 #include "asm/types.h" 13 14 /* Architecture-specific global data */ 15 struct arch_global_data { 16 #if defined(CONFIG_FSL_ESDHC) 17 u32 sdhc_clk; 18 u32 sdhc_per_clk; 19 #endif 20 #if defined(CONFIG_MPC8xx) 21 unsigned long brg_clk; 22 #endif 23 #if defined(CONFIG_CPM2) 24 /* There are many clocks on the MPC8260 - see page 9-5 */ 25 unsigned long vco_out; 26 unsigned long cpm_clk; 27 unsigned long scc_clk; 28 unsigned long brg_clk; 29 #endif 30 /* TODO: sjg@chromium.org: Should these be unslgned long? */ 31 #if defined(CONFIG_MPC83xx) 32 #ifdef CONFIG_CLK_MPC83XX 33 u32 core_clk; 34 #else 35 /* There are other clocks in the MPC83XX */ 36 u32 csb_clk; 37 # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 38 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) 39 u32 tsec1_clk; 40 u32 tsec2_clk; 41 u32 usbdr_clk; 42 # elif defined(CONFIG_ARCH_MPC8309) 43 u32 usbdr_clk; 44 # endif 45 # if defined(CONFIG_ARCH_MPC834X) 46 u32 usbmph_clk; 47 # endif /* CONFIG_ARCH_MPC834X */ 48 # if defined(CONFIG_ARCH_MPC8315) 49 u32 tdm_clk; 50 # endif 51 u32 core_clk; 52 u32 enc_clk; 53 u32 lbiu_clk; 54 u32 lclk_clk; 55 # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 56 defined(CONFIG_ARCH_MPC837X) 57 u32 pciexp1_clk; 58 u32 pciexp2_clk; 59 # endif 60 # if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) 61 u32 sata_clk; 62 # endif 63 # if defined(CONFIG_ARCH_MPC8360) 64 u32 mem_sec_clk; 65 # endif /* CONFIG_ARCH_MPC8360 */ 66 #endif 67 #endif 68 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) 69 u32 lbc_clk; 70 void *cpu; 71 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ 72 #if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ 73 defined(CONFIG_MPC86xx) 74 u32 i2c1_clk; 75 u32 i2c2_clk; 76 #endif 77 #if defined(CONFIG_QE) 78 u32 qe_clk; 79 u32 brg_clk; 80 uint mp_alloc_base; 81 uint mp_alloc_top; 82 #endif /* CONFIG_QE */ 83 #if defined(CONFIG_FSL_LAW) 84 u32 used_laws; 85 #endif 86 #if defined(CONFIG_E500) 87 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; 88 #endif 89 unsigned long reset_status; /* reset status register at boot */ 90 #if defined(CONFIG_MPC83xx) 91 unsigned long arbiter_event_attributes; 92 unsigned long arbiter_event_address; 93 #endif 94 #if defined(CONFIG_CPM2) 95 unsigned int dp_alloc_base; 96 unsigned int dp_alloc_top; 97 #endif 98 #ifdef CONFIG_SYS_FPGA_COUNT 99 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; 100 #endif 101 #if defined(CONFIG_WD_MAX_RATE) 102 unsigned long long wdt_last; /* trace watch-dog triggering rate */ 103 #endif 104 #if defined(CONFIG_LWMON5) 105 unsigned long kbd_status; 106 #endif 107 }; 108 109 #include <asm-generic/global_data.h> 110 111 #if 1 112 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") 113 #else /* We could use plain global data, but the resulting code is bigger */ 114 #define XTRN_DECLARE_GLOBAL_DATA_PTR extern 115 #define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ 116 gd_t *gd 117 #endif 118 119 #endif /* __ASM_GBL_DATA_H */ 120