1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale SerDes initialization routine
4 *
5 * Copyright 2007,2011 Freescale Semiconductor, Inc.
6 * Copyright (C) 2008 MontaVista Software, Inc.
7 *
8 * Author: Li Yang <leoli@freescale.com>
9 */
10
11 #ifndef CONFIG_MPC83XX_SERDES
12
13 #include <config.h>
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/fsl_mpc83xx_serdes.h>
17 #include <linux/delay.h>
18
19 /* SerDes registers */
20 #define FSL_SRDSCR0_OFFS 0x0
21 #define FSL_SRDSCR0_DPP_1V2 0x00008800
22 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
23 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
24 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
25 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
26 #define FSL_SRDSCR1_OFFS 0x4
27 #define FSL_SRDSCR1_PLLBW 0x00000040
28 #define FSL_SRDSCR2_OFFS 0x8
29 #define FSL_SRDSCR2_VDD_1V2 0x00800000
30 #define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
31 #define FSL_SRDSCR2_SEIC_SATA 0x00001414
32 #define FSL_SRDSCR2_SEIC_PEX 0x00001010
33 #define FSL_SRDSCR2_SEIC_SGMII 0x00000101
34 #define FSL_SRDSCR3_OFFS 0xc
35 #define FSL_SRDSCR3_KFR_SATA 0x10100000
36 #define FSL_SRDSCR3_KPH_SATA 0x04040000
37 #define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
38 #define FSL_SRDSCR3_SDTXL_SATA 0x00000505
39 #define FSL_SRDSCR4_OFFS 0x10
40 #define FSL_SRDSCR4_PROT_SATA 0x00000808
41 #define FSL_SRDSCR4_PROT_PEX 0x00000101
42 #define FSL_SRDSCR4_PROT_SGMII 0x00000505
43 #define FSL_SRDSCR4_PLANE_X2 0x01000000
44 #define FSL_SRDSRSTCTL_OFFS 0x20
45 #define FSL_SRDSRSTCTL_RST 0x80000000
46 #define FSL_SRDSRSTCTL_SATA_RESET 0xf
47
fsl_setup_serdes(u32 offset,char proto,u32 rfcks,char vdd)48 void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
49 {
50 void *regs = (void *)CONFIG_SYS_IMMR + offset;
51 u32 tmp;
52
53 /* 1.0V corevdd */
54 if (vdd) {
55 /* DPPE/DPPA = 0 */
56 tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
57 tmp &= ~FSL_SRDSCR0_DPP_1V2;
58 out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
59
60 /* VDD = 0 */
61 tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
62 tmp &= ~FSL_SRDSCR2_VDD_1V2;
63 out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
64 }
65
66 /* protocol specific configuration */
67 switch (proto) {
68 case FSL_SERDES_PROTO_SATA:
69 /* Set and clear reset bits */
70 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
71 tmp |= FSL_SRDSRSTCTL_SATA_RESET;
72 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
73 udelay(1000);
74 tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
75 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
76
77 /* Configure SRDSCR0 */
78 clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
79 FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
80 FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
81
82 /* Configure SRDSCR1 */
83 tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
84 tmp &= ~FSL_SRDSCR1_PLLBW;
85 out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
86
87 /* Configure SRDSCR2 */
88 tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
89 tmp &= ~FSL_SRDSCR2_SEIC_MASK;
90 tmp |= FSL_SRDSCR2_SEIC_SATA;
91 out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
92
93 /* Configure SRDSCR3 */
94 tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
95 FSL_SRDSCR3_SDFM_SATA_PEX |
96 FSL_SRDSCR3_SDTXL_SATA;
97 out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
98
99 /* Configure SRDSCR4 */
100 tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
101 out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
102 break;
103 case FSL_SERDES_PROTO_PEX:
104 case FSL_SERDES_PROTO_PEX_X2:
105 /* Configure SRDSCR1 */
106 tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
107 tmp |= FSL_SRDSCR1_PLLBW;
108 out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
109
110 /* Configure SRDSCR2 */
111 tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
112 tmp &= ~FSL_SRDSCR2_SEIC_MASK;
113 tmp |= FSL_SRDSCR2_SEIC_PEX;
114 out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
115
116 /* Configure SRDSCR3 */
117 tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
118 out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
119
120 /* Configure SRDSCR4 */
121 tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
122 if (proto == FSL_SERDES_PROTO_PEX_X2)
123 tmp |= FSL_SRDSCR4_PLANE_X2;
124 out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
125 break;
126 case FSL_SERDES_PROTO_SGMII:
127 /* Configure SRDSCR1 */
128 tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
129 tmp &= ~FSL_SRDSCR1_PLLBW;
130 out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
131
132 /* Configure SRDSCR2 */
133 tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
134 tmp &= ~FSL_SRDSCR2_SEIC_MASK;
135 tmp |= FSL_SRDSCR2_SEIC_SGMII;
136 out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
137
138 /* Configure SRDSCR3 */
139 out_be32(regs + FSL_SRDSCR3_OFFS, 0);
140
141 /* Configure SRDSCR4 */
142 tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
143 out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
144 break;
145 default:
146 return;
147 }
148
149 /* Do a software reset */
150 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
151 tmp |= FSL_SRDSRSTCTL_RST;
152 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
153 }
154
155 #endif /* !CONFIG_MPC83XX_SERDES */
156