1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RCar Gen3 CPG MSSR driver
4 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
11 */
12
13 #include <common.h>
14 #include <clk-uclass.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <log.h>
18 #include <wait_bit.h>
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <linux/bitops.h>
22
23 #include <dt-bindings/clock/renesas-cpg-mssr.h>
24
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
27
28 #define CPG_RST_MODEMR 0x0060
29
30 #define CPG_PLL0CR 0x00d8
31 #define CPG_PLL2CR 0x002c
32 #define CPG_PLL4CR 0x01f4
33
34 #define CPG_RPC_PREDIV_MASK 0x3
35 #define CPG_RPC_PREDIV_OFFSET 3
36 #define CPG_RPC_POSTDIV_MASK 0x7
37 #define CPG_RPC_POSTDIV_OFFSET 0
38
39 /*
40 * SDn Clock
41 */
42 #define CPG_SD_STP_HCK BIT(9)
43 #define CPG_SD_STP_CK BIT(8)
44
45 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
46 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
47
48 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
49 { \
50 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
51 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
52 ((sd_srcfc) << 2) | \
53 ((sd_fc) << 0), \
54 .div = (sd_div), \
55 }
56
57 struct sd_div_table {
58 u32 val;
59 unsigned int div;
60 };
61
62 /* SDn divider
63 * sd_srcfc sd_fc div
64 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
65 *-------------------------------------------------------------------
66 * 0 0 0 (1) 1 (4) 4
67 * 0 0 1 (2) 1 (4) 8
68 * 1 0 2 (4) 1 (4) 16
69 * 1 0 3 (8) 1 (4) 32
70 * 1 0 4 (16) 1 (4) 64
71 * 0 0 0 (1) 0 (2) 2
72 * 0 0 1 (2) 0 (2) 4
73 * 1 0 2 (4) 0 (2) 8
74 * 1 0 3 (8) 0 (2) 16
75 * 1 0 4 (16) 0 (2) 32
76 */
77 static const struct sd_div_table cpg_sd_div_table[] = {
78 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
79 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
80 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
81 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
82 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
83 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
84 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
85 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
86 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
87 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
88 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
89 };
90
gen3_clk_get_parent(struct gen3_clk_priv * priv,struct clk * clk,struct cpg_mssr_info * info,struct clk * parent)91 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
92 struct cpg_mssr_info *info, struct clk *parent)
93 {
94 const struct cpg_core_clk *core;
95 int ret;
96
97 if (!renesas_clk_is_mod(clk)) {
98 ret = renesas_clk_get_core(clk, info, &core);
99 if (ret)
100 return ret;
101
102 if (core->type == CLK_TYPE_GEN3_MDSEL) {
103 parent->dev = clk->dev;
104 parent->id = core->parent >> (priv->sscg ? 16 : 0);
105 parent->id &= 0xffff;
106 return 0;
107 }
108 }
109
110 return renesas_clk_get_parent(clk, info, parent);
111 }
112
gen3_clk_setup_sdif_div(struct clk * clk,ulong rate)113 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
114 {
115 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
116 struct cpg_mssr_info *info = priv->info;
117 const struct cpg_core_clk *core;
118 struct clk parent;
119 int ret;
120
121 ret = gen3_clk_get_parent(priv, clk, info, &parent);
122 if (ret) {
123 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
124 return ret;
125 }
126
127 if (renesas_clk_is_mod(&parent))
128 return 0;
129
130 ret = renesas_clk_get_core(&parent, info, &core);
131 if (ret)
132 return ret;
133
134 if (core->type != CLK_TYPE_GEN3_SD)
135 return 0;
136
137 debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
138
139 writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
140
141 return 0;
142 }
143
gen3_clk_enable(struct clk * clk)144 static int gen3_clk_enable(struct clk *clk)
145 {
146 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
147
148 return renesas_clk_endisable(clk, priv->base, true);
149 }
150
gen3_clk_disable(struct clk * clk)151 static int gen3_clk_disable(struct clk *clk)
152 {
153 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
154
155 return renesas_clk_endisable(clk, priv->base, false);
156 }
157
gen3_clk_get_rate64(struct clk * clk)158 static u64 gen3_clk_get_rate64(struct clk *clk)
159 {
160 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
161 struct cpg_mssr_info *info = priv->info;
162 struct clk parent;
163 const struct cpg_core_clk *core;
164 const struct rcar_gen3_cpg_pll_config *pll_config =
165 priv->cpg_pll_config;
166 u32 value, mult, div, prediv, postdiv;
167 u64 rate = 0;
168 int i, ret;
169
170 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
171
172 ret = gen3_clk_get_parent(priv, clk, info, &parent);
173 if (ret) {
174 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
175 return ret;
176 }
177
178 if (renesas_clk_is_mod(clk)) {
179 rate = gen3_clk_get_rate64(&parent);
180 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
181 __func__, __LINE__, parent.id, rate);
182 return rate;
183 }
184
185 ret = renesas_clk_get_core(clk, info, &core);
186 if (ret)
187 return ret;
188
189 switch (core->type) {
190 case CLK_TYPE_IN:
191 if (core->id == info->clk_extal_id) {
192 rate = clk_get_rate(&priv->clk_extal);
193 debug("%s[%i] EXTAL clk: rate=%llu\n",
194 __func__, __LINE__, rate);
195 return rate;
196 }
197
198 if (core->id == info->clk_extalr_id) {
199 rate = clk_get_rate(&priv->clk_extalr);
200 debug("%s[%i] EXTALR clk: rate=%llu\n",
201 __func__, __LINE__, rate);
202 return rate;
203 }
204
205 return -EINVAL;
206
207 case CLK_TYPE_GEN3_MAIN:
208 rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
209 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
210 __func__, __LINE__,
211 core->parent, pll_config->extal_div, rate);
212 return rate;
213
214 case CLK_TYPE_GEN3_PLL0:
215 value = readl(priv->base + CPG_PLL0CR);
216 mult = (((value >> 24) & 0x7f) + 1) * 2;
217 rate = gen3_clk_get_rate64(&parent) * mult;
218 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
219 __func__, __LINE__, core->parent, mult, rate);
220 return rate;
221
222 case CLK_TYPE_GEN3_PLL1:
223 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
224 rate /= pll_config->pll1_div;
225 debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
226 __func__, __LINE__,
227 core->parent, pll_config->pll1_mult,
228 pll_config->pll1_div, rate);
229 return rate;
230
231 case CLK_TYPE_GEN3_PLL2:
232 value = readl(priv->base + CPG_PLL2CR);
233 mult = (((value >> 24) & 0x7f) + 1) * 2;
234 rate = gen3_clk_get_rate64(&parent) * mult;
235 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
236 __func__, __LINE__, core->parent, mult, rate);
237 return rate;
238
239 case CLK_TYPE_GEN3_PLL3:
240 rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
241 rate /= pll_config->pll3_div;
242 debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
243 __func__, __LINE__,
244 core->parent, pll_config->pll3_mult,
245 pll_config->pll3_div, rate);
246 return rate;
247
248 case CLK_TYPE_GEN3_PLL4:
249 value = readl(priv->base + CPG_PLL4CR);
250 mult = (((value >> 24) & 0x7f) + 1) * 2;
251 rate = gen3_clk_get_rate64(&parent) * mult;
252 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
253 __func__, __LINE__, core->parent, mult, rate);
254 return rate;
255
256 case CLK_TYPE_FF:
257 rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
258 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
259 __func__, __LINE__,
260 core->parent, core->mult, core->div, rate);
261 return rate;
262
263 case CLK_TYPE_GEN3_MDSEL:
264 div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
265 rate = gen3_clk_get_rate64(&parent) / div;
266 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
267 __func__, __LINE__,
268 (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
269 div, rate);
270 return rate;
271
272 case CLK_TYPE_GEN3_SD: /* FIXME */
273 value = readl(priv->base + core->offset);
274 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
275
276 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
277 if (cpg_sd_div_table[i].val != value)
278 continue;
279
280 rate = gen3_clk_get_rate64(&parent) /
281 cpg_sd_div_table[i].div;
282 debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
283 __func__, __LINE__,
284 core->parent, cpg_sd_div_table[i].div, rate);
285
286 return rate;
287 }
288
289 return -EINVAL;
290
291 case CLK_TYPE_GEN3_RPC:
292 rate = gen3_clk_get_rate64(&parent);
293
294 value = readl(priv->base + core->offset);
295
296 prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
297 CPG_RPC_PREDIV_MASK;
298 if (prediv == 2)
299 rate /= 5;
300 else if (prediv == 3)
301 rate /= 6;
302 else
303 return -EINVAL;
304
305 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
306 CPG_RPC_POSTDIV_MASK;
307 rate /= postdiv + 1;
308
309 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
310 __func__, __LINE__,
311 core->parent, prediv, postdiv, rate);
312
313 return -EINVAL;
314
315 }
316
317 printf("%s[%i] unknown fail\n", __func__, __LINE__);
318
319 return -ENOENT;
320 }
321
gen3_clk_get_rate(struct clk * clk)322 static ulong gen3_clk_get_rate(struct clk *clk)
323 {
324 return gen3_clk_get_rate64(clk);
325 }
326
gen3_clk_set_rate(struct clk * clk,ulong rate)327 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
328 {
329 /* Force correct SD-IF divider configuration if applicable */
330 gen3_clk_setup_sdif_div(clk, rate);
331 return gen3_clk_get_rate64(clk);
332 }
333
gen3_clk_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)334 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
335 {
336 if (args->args_count != 2) {
337 debug("Invaild args_count: %d\n", args->args_count);
338 return -EINVAL;
339 }
340
341 clk->id = (args->args[0] << 16) | args->args[1];
342
343 return 0;
344 }
345
346 const struct clk_ops gen3_clk_ops = {
347 .enable = gen3_clk_enable,
348 .disable = gen3_clk_disable,
349 .get_rate = gen3_clk_get_rate,
350 .set_rate = gen3_clk_set_rate,
351 .of_xlate = gen3_clk_of_xlate,
352 };
353
gen3_clk_probe(struct udevice * dev)354 int gen3_clk_probe(struct udevice *dev)
355 {
356 struct gen3_clk_priv *priv = dev_get_priv(dev);
357 struct cpg_mssr_info *info =
358 (struct cpg_mssr_info *)dev_get_driver_data(dev);
359 fdt_addr_t rst_base;
360 u32 cpg_mode;
361 int ret;
362
363 priv->base = dev_read_addr_ptr(dev);
364 if (!priv->base)
365 return -EINVAL;
366
367 priv->info = info;
368 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
369 if (ret < 0)
370 return ret;
371
372 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
373 if (rst_base == FDT_ADDR_T_NONE)
374 return -EINVAL;
375
376 cpg_mode = readl(rst_base + CPG_RST_MODEMR);
377
378 priv->cpg_pll_config =
379 (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
380 if (!priv->cpg_pll_config->extal_div)
381 return -EINVAL;
382
383 priv->sscg = !(cpg_mode & BIT(12));
384
385 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
386 if (ret < 0)
387 return ret;
388
389 if (info->extalr_node) {
390 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
391 if (ret < 0)
392 return ret;
393 }
394
395 return 0;
396 }
397
gen3_clk_remove(struct udevice * dev)398 int gen3_clk_remove(struct udevice *dev)
399 {
400 struct gen3_clk_priv *priv = dev_get_priv(dev);
401
402 return renesas_clk_remove(priv->base, priv->info);
403 }
404