1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * Driver for GIC-500 and GIC-600 specific features. This driver only
10 * overrides APIs that are different to those generic ones in GICv3
11 * driver.
12 *
13 * GIC-600 supports independently power-gating redistributor interface.
14 */
15
16 #include <assert.h>
17
18 #include <arch_helpers.h>
19 #include <drivers/arm/arm_gicv3_common.h>
20 #include <drivers/arm/gicv3.h>
21
22 #include "gicv3_private.h"
23
24 /* GIC-600 specific register offsets */
25 #define GICR_PWRR 0x24U
26
27 /* GICR_PWRR fields */
28 #define PWRR_RDPD_SHIFT 0
29 #define PWRR_RDAG_SHIFT 1
30 #define PWRR_RDGPD_SHIFT 2
31 #define PWRR_RDGPO_SHIFT 3
32
33 #define PWRR_RDPD (1U << PWRR_RDPD_SHIFT)
34 #define PWRR_RDAG (1U << PWRR_RDAG_SHIFT)
35 #define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT)
36 #define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT)
37
38 /*
39 * Values to write to GICR_PWRR register to power redistributor
40 * for operating through the core (GICR_PWRR.RDAG = 0)
41 */
42 #define PWRR_ON (0U << PWRR_RDPD_SHIFT)
43 #define PWRR_OFF (1U << PWRR_RDPD_SHIFT)
44
45 #if GICV3_SUPPORT_GIC600
46
47 /* GIC-600/700 specific accessor functions */
gicr_write_pwrr(uintptr_t base,unsigned int val)48 static void gicr_write_pwrr(uintptr_t base, unsigned int val)
49 {
50 mmio_write_32(base + GICR_PWRR, val);
51 }
52
gicr_read_pwrr(uintptr_t base)53 static uint32_t gicr_read_pwrr(uintptr_t base)
54 {
55 return mmio_read_32(base + GICR_PWRR);
56 }
57
gicr_wait_group_not_in_transit(uintptr_t base)58 static void gicr_wait_group_not_in_transit(uintptr_t base)
59 {
60 uint32_t pwrr;
61
62 do {
63 pwrr = gicr_read_pwrr(base);
64
65 /* Check group not transitioning: RDGPD == RDGPO */
66 } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
67 ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT));
68 }
69
gic600_pwr_on(uintptr_t base)70 static void gic600_pwr_on(uintptr_t base)
71 {
72 do { /* Wait until group not transitioning */
73 gicr_wait_group_not_in_transit(base);
74
75 /* Power on redistributor */
76 gicr_write_pwrr(base, PWRR_ON);
77
78 /*
79 * Wait until the power on state is reflected.
80 * If RDPD == 0 then powered on.
81 */
82 } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON);
83 }
84
gic600_pwr_off(uintptr_t base)85 static void gic600_pwr_off(uintptr_t base)
86 {
87 /* Wait until group not transitioning */
88 gicr_wait_group_not_in_transit(base);
89
90 /* Power off redistributor */
91 gicr_write_pwrr(base, PWRR_OFF);
92
93 /*
94 * If this is the last man, turning this redistributor frame off will
95 * result in the group itself being powered off and RDGPD = 1.
96 * In that case, wait as long as it's in transition, or has aborted
97 * the transition altogether for any reason.
98 */
99 if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) {
100 /* Wait until group not transitioning */
101 gicr_wait_group_not_in_transit(base);
102 }
103 }
104
get_gicr_base(unsigned int proc_num)105 static uintptr_t get_gicr_base(unsigned int proc_num)
106 {
107 uintptr_t gicr_base;
108
109 assert(gicv3_driver_data != NULL);
110 assert(proc_num < gicv3_driver_data->rdistif_num);
111 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
112
113 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
114 assert(gicr_base != 0UL);
115
116 return gicr_base;
117 }
118
gicv3_redists_need_power_mgmt(uintptr_t gicr_base)119 static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base)
120 {
121 uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR);
122
123 /*
124 * The Arm GIC-600 and GIC-700 models have their redistributors
125 * powered down at reset.
126 */
127 return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) ||
128 ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE) ||
129 ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_700));
130 }
131
132 #endif /* GICV3_SUPPORT_GIC600 */
133
gicv3_distif_pre_save(unsigned int proc_num)134 void gicv3_distif_pre_save(unsigned int proc_num)
135 {
136 arm_gicv3_distif_pre_save(proc_num);
137 }
138
gicv3_distif_post_restore(unsigned int proc_num)139 void gicv3_distif_post_restore(unsigned int proc_num)
140 {
141 arm_gicv3_distif_post_restore(proc_num);
142 }
143
144 /*
145 * Power off GIC-600 redistributor (if configured and detected)
146 */
gicv3_rdistif_off(unsigned int proc_num)147 void gicv3_rdistif_off(unsigned int proc_num)
148 {
149 #if GICV3_SUPPORT_GIC600
150 uintptr_t gicr_base = get_gicr_base(proc_num);
151
152 /* Attempt to power redistributor off */
153 if (gicv3_redists_need_power_mgmt(gicr_base)) {
154 gic600_pwr_off(gicr_base);
155 }
156 #endif
157 }
158
159 /*
160 * Power on GIC-600 redistributor (if configured and detected)
161 */
gicv3_rdistif_on(unsigned int proc_num)162 void gicv3_rdistif_on(unsigned int proc_num)
163 {
164 #if GICV3_SUPPORT_GIC600
165 uintptr_t gicr_base = get_gicr_base(proc_num);
166
167 /* Power redistributor on */
168 if (gicv3_redists_need_power_mgmt(gicr_base)) {
169 gic600_pwr_on(gicr_base);
170 }
171 #endif
172 }
173