1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/net/ti-dp83867.h>
9
10/ {
11	memory@40000000 {
12		device_type = "memory";
13		reg = <0x0 0x40000000 0 0x80000000>;
14	};
15
16	gpio-keys {
17		compatible = "gpio-keys";
18
19		user-pb {
20			label = "user_pb";
21			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
22			linux,code = <BTN_0>;
23		};
24
25		user-pb1x {
26			label = "user_pb1x";
27			linux,code = <BTN_1>;
28			interrupt-parent = <&gsc>;
29			interrupts = <0>;
30		};
31
32		key-erased {
33			label = "key_erased";
34			linux,code = <BTN_2>;
35			interrupt-parent = <&gsc>;
36			interrupts = <1>;
37		};
38
39		eeprom-wp {
40			label = "eeprom_wp";
41			linux,code = <BTN_3>;
42			interrupt-parent = <&gsc>;
43			interrupts = <2>;
44		};
45
46		tamper {
47			label = "tamper";
48			linux,code = <BTN_4>;
49			interrupt-parent = <&gsc>;
50			interrupts = <5>;
51		};
52
53		switch-hold {
54			label = "switch_hold";
55			linux,code = <BTN_5>;
56			interrupt-parent = <&gsc>;
57			interrupts = <7>;
58		};
59	};
60};
61
62&A53_0 {
63	cpu-supply = <&buck3_reg>;
64};
65
66&A53_1 {
67	cpu-supply = <&buck3_reg>;
68};
69
70&A53_2 {
71	cpu-supply = <&buck3_reg>;
72};
73
74&A53_3 {
75	cpu-supply = <&buck3_reg>;
76};
77
78&ddrc {
79	operating-points-v2 = <&ddrc_opp_table>;
80
81	ddrc_opp_table: opp-table {
82		compatible = "operating-points-v2";
83
84		opp-25M {
85			opp-hz = /bits/ 64 <25000000>;
86		};
87
88		opp-100M {
89			opp-hz = /bits/ 64 <100000000>;
90		};
91
92		opp-750M {
93			opp-hz = /bits/ 64 <750000000>;
94		};
95	};
96};
97
98&fec1 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_fec1>;
101	phy-mode = "rgmii-id";
102	phy-handle = <&ethphy0>;
103	status = "okay";
104
105	mdio {
106		#address-cells = <1>;
107		#size-cells = <0>;
108
109		ethphy0: ethernet-phy@0 {
110			compatible = "ethernet-phy-ieee802.3-c22";
111			reg = <0>;
112			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
113			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
114			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
115			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
116		};
117	};
118};
119
120&i2c1 {
121	clock-frequency = <100000>;
122	pinctrl-names = "default";
123	pinctrl-0 = <&pinctrl_i2c1>;
124	status = "okay";
125
126	gsc: gsc@20 {
127		compatible = "gw,gsc";
128		reg = <0x20>;
129		pinctrl-0 = <&pinctrl_gsc>;
130		interrupt-parent = <&gpio2>;
131		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
132		interrupt-controller;
133		#interrupt-cells = <1>;
134		#address-cells = <1>;
135		#size-cells = <0>;
136
137		adc {
138			compatible = "gw,gsc-adc";
139			#address-cells = <1>;
140			#size-cells = <0>;
141
142			channel@6 {
143				gw,mode = <0>;
144				reg = <0x06>;
145				label = "temp";
146			};
147
148			channel@8 {
149				gw,mode = <1>;
150				reg = <0x08>;
151				label = "vdd_bat";
152			};
153
154			channel@16 {
155				gw,mode = <4>;
156				reg = <0x16>;
157				label = "fan_tach";
158			};
159
160			channel@82 {
161				gw,mode = <2>;
162				reg = <0x82>;
163				label = "vdd_vin";
164				gw,voltage-divider-ohms = <22100 1000>;
165			};
166
167			channel@84 {
168				gw,mode = <2>;
169				reg = <0x84>;
170				label = "vdd_adc1";
171				gw,voltage-divider-ohms = <10000 10000>;
172			};
173
174			channel@86 {
175				gw,mode = <2>;
176				reg = <0x86>;
177				label = "vdd_adc2";
178				gw,voltage-divider-ohms = <10000 10000>;
179			};
180
181			channel@88 {
182				gw,mode = <2>;
183				reg = <0x88>;
184				label = "vdd_dram";
185			};
186
187			channel@8c {
188				gw,mode = <2>;
189				reg = <0x8c>;
190				label = "vdd_1p2";
191			};
192
193			channel@8e {
194				gw,mode = <2>;
195				reg = <0x8e>;
196				label = "vdd_1p0";
197			};
198
199			channel@90 {
200				gw,mode = <2>;
201				reg = <0x90>;
202				label = "vdd_2p5";
203				gw,voltage-divider-ohms = <10000 10000>;
204			};
205
206			channel@92 {
207				gw,mode = <2>;
208				reg = <0x92>;
209				label = "vdd_3p3";
210				gw,voltage-divider-ohms = <10000 10000>;
211			};
212
213			channel@98 {
214				gw,mode = <2>;
215				reg = <0x98>;
216				label = "vdd_0p95";
217			};
218
219			channel@9a {
220				gw,mode = <2>;
221				reg = <0x9a>;
222				label = "vdd_1p8";
223			};
224
225			channel@a2 {
226				gw,mode = <2>;
227				reg = <0xa2>;
228				label = "vdd_gsc";
229				gw,voltage-divider-ohms = <10000 10000>;
230			};
231		};
232
233		fan-controller@0 {
234			#address-cells = <1>;
235			#size-cells = <0>;
236			compatible = "gw,gsc-fan";
237			reg = <0x0a>;
238		};
239	};
240
241	gpio: gpio@23 {
242		compatible = "nxp,pca9555";
243		reg = <0x23>;
244		gpio-controller;
245		#gpio-cells = <2>;
246		interrupt-parent = <&gsc>;
247		interrupts = <4>;
248	};
249
250	eeprom@50 {
251		compatible = "atmel,24c02";
252		reg = <0x50>;
253		pagesize = <16>;
254	};
255
256	eeprom@51 {
257		compatible = "atmel,24c02";
258		reg = <0x51>;
259		pagesize = <16>;
260	};
261
262	eeprom@52 {
263		compatible = "atmel,24c02";
264		reg = <0x52>;
265		pagesize = <16>;
266	};
267
268	eeprom@53 {
269		compatible = "atmel,24c02";
270		reg = <0x53>;
271		pagesize = <16>;
272	};
273
274	rtc@68 {
275		compatible = "dallas,ds1672";
276		reg = <0x68>;
277	};
278
279	pmic@69 {
280		compatible = "mps,mp5416";
281		pinctrl-names = "default";
282		pinctrl-0 = <&pinctrl_pmic>;
283		reg = <0x69>;
284
285		regulators {
286			buck1 {
287				regulator-name = "vdd_0p95";
288				regulator-min-microvolt = <805000>;
289				regulator-max-microvolt = <1000000>;
290				regulator-max-microamp = <2500000>;
291				regulator-boot-on;
292			};
293
294			buck2 {
295				regulator-name = "vdd_soc";
296				regulator-min-microvolt = <805000>;
297				regulator-max-microvolt = <900000>;
298				regulator-max-microamp = <1000000>;
299				regulator-boot-on;
300			};
301
302			buck3_reg: buck3 {
303				regulator-name = "vdd_arm";
304				regulator-min-microvolt = <805000>;
305				regulator-max-microvolt = <1000000>;
306				regulator-max-microamp = <2200000>;
307				regulator-boot-on;
308			};
309
310			buck4 {
311				regulator-name = "vdd_1p8";
312				regulator-min-microvolt = <1800000>;
313				regulator-max-microvolt = <1800000>;
314				regulator-max-microamp = <500000>;
315				regulator-boot-on;
316			};
317
318			ldo1 {
319				regulator-name = "nvcc_snvs_1p8";
320				regulator-min-microvolt = <1800000>;
321				regulator-max-microvolt = <1800000>;
322				regulator-max-microamp = <300000>;
323				regulator-boot-on;
324			};
325
326			ldo2 {
327				regulator-name = "vdd_snvs_0p8";
328				regulator-min-microvolt = <800000>;
329				regulator-max-microvolt = <800000>;
330				regulator-boot-on;
331			};
332
333			ldo3 {
334				regulator-name = "vdd_0p95";
335				regulator-min-microvolt = <800000>;
336				regulator-max-microvolt = <800000>;
337				regulator-boot-on;
338			};
339
340			ldo4 {
341				regulator-name = "vdd_1p8";
342				regulator-min-microvolt = <1800000>;
343				regulator-max-microvolt = <1800000>;
344				regulator-boot-on;
345			};
346		};
347	};
348};
349
350&i2c2 {
351	clock-frequency = <400000>;
352	pinctrl-names = "default";
353	pinctrl-0 = <&pinctrl_i2c2>;
354	status = "okay";
355
356	eeprom@52 {
357		compatible = "atmel,24c32";
358		reg = <0x52>;
359		pagesize = <32>;
360	};
361};
362
363/* console */
364&uart2 {
365	pinctrl-names = "default";
366	pinctrl-0 = <&pinctrl_uart2>;
367	status = "okay";
368};
369
370/* eMMC */
371&usdhc3 {
372	pinctrl-names = "default", "state_100mhz", "state_200mhz";
373	pinctrl-0 = <&pinctrl_usdhc3>;
374	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
375	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
376	bus-width = <8>;
377	non-removable;
378	status = "okay";
379};
380
381&wdog1 {
382	pinctrl-names = "default";
383	pinctrl-0 = <&pinctrl_wdog>;
384	fsl,ext-reset-output;
385	status = "okay";
386};
387
388&iomuxc {
389	pinctrl_fec1: fec1grp {
390		fsl,pins = <
391			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
392			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
393			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
394			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
395			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
396			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
397			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
398			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
399			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
400			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
401			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
402			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
403			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
404			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
405			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19
406		>;
407	};
408
409	pinctrl_gsc: gscgrp {
410		fsl,pins = <
411			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x159
412		>;
413	};
414
415	pinctrl_i2c1: i2c1grp {
416		fsl,pins = <
417			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
418			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
419		>;
420	};
421
422	pinctrl_i2c2: i2c2grp {
423		fsl,pins = <
424			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
425			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
426		>;
427	};
428
429	pinctrl_pmic: pmicgrp {
430		fsl,pins = <
431			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
432		>;
433	};
434
435	pinctrl_uart2: uart2grp {
436		fsl,pins = <
437			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
438			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
439		>;
440	};
441
442	pinctrl_usdhc3: usdhc3grp {
443		fsl,pins = <
444			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
445			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
446			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
447			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
448			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
449			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
450			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
451			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
452			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
453			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
454			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
455		>;
456	};
457
458	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
459		fsl,pins = <
460			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
461			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
462			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
463			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
464			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
465			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
466			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
467			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
468			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
469			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
470			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
471		>;
472	};
473
474	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
475		fsl,pins = <
476			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
477			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
478			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
479			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
480			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
481			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
482			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
483			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
484			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
485			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
486			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
487		>;
488	};
489
490	pinctrl_wdog: wdoggrp {
491		fsl,pins = <
492			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
493		>;
494	};
495};
496