1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/arch/arm/kernel/irq.c
4  *
5  *  Copyright (C) 1992 Linus Torvalds
6  *  Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
7  *
8  *  Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
9  *  Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
10  *  Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
11  *
12  *  This file contains the code used by various IRQ handling routines:
13  *  asking for different IRQ's should be done through these routines
14  *  instead of just grabbing them. Thus setups with different IRQ numbers
15  *  shouldn't result in any weird surprises, and installing new handlers
16  *  should be easier.
17  *
18  *  IRQ's are in fact implemented a bit like signal handlers for the kernel.
19  *  Naturally it's not a 1:1 relation, but there are similarities.
20  */
21 #include <linux/signal.h>
22 #include <linux/ioport.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqchip.h>
26 #include <linux/random.h>
27 #include <linux/smp.h>
28 #include <linux/init.h>
29 #include <linux/seq_file.h>
30 #include <linux/errno.h>
31 #include <linux/list.h>
32 #include <linux/kallsyms.h>
33 #include <linux/proc_fs.h>
34 #include <linux/export.h>
35 
36 #include <asm/hardware/cache-l2x0.h>
37 #include <asm/hardware/cache-uniphier.h>
38 #include <asm/outercache.h>
39 #include <asm/exception.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 
44 unsigned long irq_err_count;
45 
arch_show_interrupts(struct seq_file * p,int prec)46 int arch_show_interrupts(struct seq_file *p, int prec)
47 {
48 #ifdef CONFIG_FIQ
49 	show_fiq_list(p, prec);
50 #endif
51 #ifdef CONFIG_SMP
52 	show_ipi_list(p, prec);
53 #endif
54 	seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
55 	return 0;
56 }
57 
58 /*
59  * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
60  * not come via this function.  Instead, they should provide their
61  * own 'handler'.  Used by platform code implementing C-based 1st
62  * level decoding.
63  */
handle_IRQ(unsigned int irq,struct pt_regs * regs)64 void handle_IRQ(unsigned int irq, struct pt_regs *regs)
65 {
66 	struct irq_desc *desc;
67 
68 	/*
69 	 * Some hardware gives randomly wrong interrupts.  Rather
70 	 * than crashing, do something sensible.
71 	 */
72 	if (unlikely(!irq || irq >= nr_irqs))
73 		desc = NULL;
74 	else
75 		desc = irq_to_desc(irq);
76 
77 	if (likely(desc))
78 		handle_irq_desc(desc);
79 	else
80 		ack_bad_irq(irq);
81 }
82 
83 /*
84  * asm_do_IRQ is the interface to be used from assembly code.
85  */
86 asmlinkage void __exception_irq_entry
asm_do_IRQ(unsigned int irq,struct pt_regs * regs)87 asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
88 {
89 	struct pt_regs *old_regs;
90 
91 	irq_enter();
92 	old_regs = set_irq_regs(regs);
93 
94 	handle_IRQ(irq, regs);
95 
96 	set_irq_regs(old_regs);
97 	irq_exit();
98 }
99 
init_IRQ(void)100 void __init init_IRQ(void)
101 {
102 	int ret;
103 
104 	if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
105 		irqchip_init();
106 	else
107 		machine_desc->init_irq();
108 
109 	if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
110 	    (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
111 		if (!outer_cache.write_sec)
112 			outer_cache.write_sec = machine_desc->l2c_write_sec;
113 		ret = l2x0_of_init(machine_desc->l2c_aux_val,
114 				   machine_desc->l2c_aux_mask);
115 		if (ret && ret != -ENODEV)
116 			pr_err("L2C: failed to init: %d\n", ret);
117 	}
118 
119 	uniphier_cache_init();
120 }
121 
122 #ifdef CONFIG_SPARSE_IRQ
arch_probe_nr_irqs(void)123 int __init arch_probe_nr_irqs(void)
124 {
125 	nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
126 	return nr_irqs;
127 }
128 #endif
129