1 /******************************************************************************
2  * pci.h
3  *
4  * PCI access functions.
5  */
6 
7 #ifndef __XEN_PCI_H__
8 #define __XEN_PCI_H__
9 
10 #include <xen/types.h>
11 #include <xen/list.h>
12 #include <xen/spinlock.h>
13 #include <xen/irq.h>
14 #include <xen/pci_regs.h>
15 #include <xen/pfn.h>
16 #include <asm/device.h>
17 #include <asm/numa.h>
18 #include <asm/pci.h>
19 
20 /*
21  * The PCI interface treats multi-function devices as independent
22  * devices.  The slot/function address of each device is encoded
23  * in a single byte as follows:
24  *
25  * 15:8 = bus
26  *  7:3 = slot
27  *  2:0 = function
28  */
29 #define PCI_SEG(sbdf) (((sbdf) >> 16) & 0xffff)
30 #define PCI_BUS(bdf)    (((bdf) >> 8) & 0xff)
31 #define PCI_SLOT(bdf)   (((bdf) >> 3) & 0x1f)
32 #define PCI_FUNC(bdf)   ((bdf) & 0x07)
33 #define PCI_DEVFN(d,f)  ((((d) & 0x1f) << 3) | ((f) & 0x07))
34 #define PCI_DEVFN2(bdf) ((bdf) & 0xff)
35 #define PCI_BDF(b,d,f)  ((((b) & 0xff) << 8) | PCI_DEVFN(d,f))
36 #define PCI_BDF2(b,df)  ((((b) & 0xff) << 8) | ((df) & 0xff))
37 #define PCI_SBDF(s,b,d,f) \
38     ((pci_sbdf_t){ .sbdf = (((s) & 0xffff) << 16) | PCI_BDF(b, d, f) })
39 #define PCI_SBDF2(s,bdf) \
40     ((pci_sbdf_t){ .sbdf = (((s) & 0xffff) << 16) | ((bdf) & 0xffff) })
41 #define PCI_SBDF3(s,b,df) \
42     ((pci_sbdf_t){ .sbdf = (((s) & 0xffff) << 16) | PCI_BDF2(b, df) })
43 
44 typedef union {
45     uint32_t sbdf;
46     struct {
47         union {
48             uint16_t bdf;
49             struct {
50                 union {
51                     struct {
52                         uint8_t fn   : 3,
53                                 dev  : 5;
54                     };
55                     uint8_t     devfn,
56                                 extfunc;
57                 };
58                 uint8_t         bus;
59             };
60         };
61         uint16_t                seg;
62     };
63 } pci_sbdf_t;
64 
65 struct pci_dev_info {
66     /*
67      * VF's 'is_extfn' field is used to indicate whether its PF is an extended
68      * function.
69      */
70     bool_t is_extfn;
71     bool_t is_virtfn;
72     struct {
73         u8 bus;
74         u8 devfn;
75     } physfn;
76 };
77 
78 struct pci_dev {
79     struct list_head alldevs_list;
80     struct list_head domain_list;
81 
82     struct list_head msi_list;
83 
84     struct arch_msix *msix;
85 
86     struct domain *domain;
87 
88     const union {
89         struct {
90             uint8_t devfn;
91             uint8_t bus;
92             uint16_t seg;
93         };
94         pci_sbdf_t sbdf;
95     };
96 
97     uint8_t msi_maxvec;
98     uint8_t phantom_stride;
99 
100     nodeid_t node; /* NUMA node */
101 
102     /* Device to be quarantined, don't automatically re-assign to dom0 */
103     bool quarantine;
104 
105     /* Device with errata, ignore the BARs. */
106     bool ignore_bars;
107 
108     enum pdev_type {
109         DEV_TYPE_PCI_UNKNOWN,
110         DEV_TYPE_PCIe_ENDPOINT,
111         DEV_TYPE_PCIe_BRIDGE,       // PCIe root port, switch
112         DEV_TYPE_PCIe2PCI_BRIDGE,   // PCIe-to-PCI/PCIx bridge
113         DEV_TYPE_PCI2PCIe_BRIDGE,   // PCI/PCIx-to-PCIe bridge
114         DEV_TYPE_LEGACY_PCI_BRIDGE, // Legacy PCI bridge
115         DEV_TYPE_PCI_HOST_BRIDGE,   // PCI Host bridge
116         DEV_TYPE_PCI,
117     } type;
118 
119     struct pci_dev_info info;
120     struct arch_pci_dev arch;
121     struct {
122         struct list_head list;
123         unsigned int cap_pos;
124         unsigned int queue_depth;
125     } ats;
126     struct {
127         s_time_t time;
128         unsigned int count;
129 #define PT_FAULT_THRESHOLD 10
130     } fault;
131     u64 vf_rlen[6];
132 
133     /* Data for vPCI. */
134     struct vpci *vpci;
135 };
136 
137 #define for_each_pdev(domain, pdev) \
138     list_for_each_entry(pdev, &(domain)->pdev_list, domain_list)
139 
140 #define has_arch_pdevs(d) (!list_empty(&(d)->pdev_list))
141 
142 /*
143  * The pcidevs_lock protect alldevs_list, and the assignment for the
144  * devices, it also sync the access to the msi capability that is not
145  * interrupt handling related (the mask bit register).
146  */
147 
148 void pcidevs_lock(void);
149 void pcidevs_unlock(void);
150 bool_t __must_check pcidevs_locked(void);
151 bool_t __must_check pcidevs_trylock(void);
152 
153 bool_t pci_known_segment(u16 seg);
154 bool_t pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func);
155 int scan_pci_devices(void);
156 enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn);
157 int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus);
158 struct pci_dev *pci_lock_pdev(int seg, int bus, int devfn);
159 struct pci_dev *pci_lock_domain_pdev(
160     struct domain *, int seg, int bus, int devfn);
161 
162 void setup_hwdom_pci_devices(struct domain *,
163                             int (*)(u8 devfn, struct pci_dev *));
164 int pci_release_devices(struct domain *d);
165 void pci_segments_init(void);
166 int pci_add_segment(u16 seg);
167 const unsigned long *pci_get_ro_map(u16 seg);
168 int pci_add_device(u16 seg, u8 bus, u8 devfn,
169                    const struct pci_dev_info *, nodeid_t node);
170 int pci_remove_device(u16 seg, u8 bus, u8 devfn);
171 int pci_ro_device(int seg, int bus, int devfn);
172 int pci_hide_device(unsigned int seg, unsigned int bus, unsigned int devfn);
173 struct pci_dev *pci_get_pdev(int seg, int bus, int devfn);
174 struct pci_dev *pci_get_real_pdev(int seg, int bus, int devfn);
175 struct pci_dev *pci_get_pdev_by_domain(const struct domain *, int seg,
176                                        int bus, int devfn);
177 void pci_check_disable_device(u16 seg, u8 bus, u8 devfn);
178 
179 uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg);
180 uint16_t pci_conf_read16(pci_sbdf_t sbdf, unsigned int reg);
181 uint32_t pci_conf_read32(pci_sbdf_t sbdf, unsigned int reg);
182 void pci_conf_write8(pci_sbdf_t sbdf, unsigned int reg, uint8_t data);
183 void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data);
184 void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data);
185 uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes);
186 void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t data);
187 int pci_mmcfg_read(unsigned int seg, unsigned int bus,
188                    unsigned int devfn, int reg, int len, u32 *value);
189 int pci_mmcfg_write(unsigned int seg, unsigned int bus,
190                     unsigned int devfn, int reg, int len, u32 value);
191 int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap);
192 int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap);
193 int pci_find_ext_capability(int seg, int bus, int devfn, int cap);
194 int pci_find_next_ext_capability(int seg, int bus, int devfn, int pos, int cap);
195 const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus,
196                       unsigned int *dev, unsigned int *func);
197 const char *parse_pci_seg(const char *, unsigned int *seg, unsigned int *bus,
198                           unsigned int *dev, unsigned int *func, bool *def_seg);
199 
200 #define PCI_BAR_VF      (1u << 0)
201 #define PCI_BAR_LAST    (1u << 1)
202 #define PCI_BAR_ROM     (1u << 2)
203 unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos,
204                               uint64_t *paddr, uint64_t *psize,
205                               unsigned int flags);
206 
207 void pci_intx(const struct pci_dev *, bool enable);
208 bool_t pcie_aer_get_firmware_first(const struct pci_dev *);
209 
210 struct pirq;
211 int msixtbl_pt_register(struct domain *, struct pirq *, uint64_t gtable);
212 void msixtbl_pt_unregister(struct domain *, struct pirq *);
213 void msixtbl_pt_cleanup(struct domain *d);
214 
215 #endif /* __XEN_PCI_H__ */
216