1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #ifndef __HDMI_CONNECTOR_H__
8 #define __HDMI_CONNECTOR_H__
9 
10 #include <linux/i2c.h>
11 #include <linux/clk.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/hdmi.h>
16 
17 #include <drm/drm_bridge.h>
18 
19 #include "msm_drv.h"
20 #include "hdmi.xml.h"
21 
22 #define HDMI_MAX_NUM_GPIO	6
23 
24 struct hdmi_phy;
25 struct hdmi_platform_config;
26 
27 struct hdmi_gpio_data {
28 	struct gpio_desc *gpiod;
29 	bool output;
30 	int value;
31 };
32 
33 struct hdmi_audio {
34 	bool enabled;
35 	struct hdmi_audio_infoframe infoframe;
36 	int rate;
37 };
38 
39 struct hdmi_hdcp_ctrl;
40 
41 struct hdmi {
42 	struct drm_device *dev;
43 	struct platform_device *pdev;
44 	struct platform_device *audio_pdev;
45 
46 	const struct hdmi_platform_config *config;
47 
48 	/* audio state: */
49 	struct hdmi_audio audio;
50 
51 	/* video state: */
52 	bool power_on;
53 	unsigned long int pixclock;
54 
55 	void __iomem *mmio;
56 	void __iomem *qfprom_mmio;
57 	phys_addr_t mmio_phy_addr;
58 
59 	struct regulator_bulk_data *hpd_regs;
60 	struct regulator_bulk_data *pwr_regs;
61 	struct clk **hpd_clks;
62 	struct clk **pwr_clks;
63 
64 	struct hdmi_phy *phy;
65 	struct device *phy_dev;
66 
67 	struct i2c_adapter *i2c;
68 	struct drm_connector *connector;
69 	struct drm_bridge *bridge;
70 
71 	/* the encoder we are hooked to (outside of hdmi block) */
72 	struct drm_encoder *encoder;
73 
74 	bool hdmi_mode;               /* are we in hdmi mode? */
75 
76 	int irq;
77 	struct workqueue_struct *workq;
78 
79 	struct hdmi_hdcp_ctrl *hdcp_ctrl;
80 
81 	/*
82 	* spinlock to protect registers shared by different execution
83 	* REG_HDMI_CTRL
84 	* REG_HDMI_DDC_ARBITRATION
85 	* REG_HDMI_HDCP_INT_CTRL
86 	* REG_HDMI_HPD_CTRL
87 	*/
88 	spinlock_t reg_lock;
89 };
90 
91 /* platform config data (ie. from DT, or pdata) */
92 struct hdmi_platform_config {
93 	const char *mmio_name;
94 	const char *qfprom_mmio_name;
95 
96 	/* regulators that need to be on for hpd: */
97 	const char **hpd_reg_names;
98 	int hpd_reg_cnt;
99 
100 	/* regulators that need to be on for screen pwr: */
101 	const char **pwr_reg_names;
102 	int pwr_reg_cnt;
103 
104 	/* clks that need to be on for hpd: */
105 	const char **hpd_clk_names;
106 	const long unsigned *hpd_freq;
107 	int hpd_clk_cnt;
108 
109 	/* clks that need to be on for screen pwr (ie pixel clk): */
110 	const char **pwr_clk_names;
111 	int pwr_clk_cnt;
112 
113 	/* gpio's: */
114 	struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
115 };
116 
117 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
118 
hdmi_write(struct hdmi * hdmi,u32 reg,u32 data)119 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
120 {
121 	msm_writel(data, hdmi->mmio + reg);
122 }
123 
hdmi_read(struct hdmi * hdmi,u32 reg)124 static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
125 {
126 	return msm_readl(hdmi->mmio + reg);
127 }
128 
hdmi_qfprom_read(struct hdmi * hdmi,u32 reg)129 static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
130 {
131 	return msm_readl(hdmi->qfprom_mmio + reg);
132 }
133 
134 /*
135  * hdmi phy:
136  */
137 
138 enum hdmi_phy_type {
139 	MSM_HDMI_PHY_8x60,
140 	MSM_HDMI_PHY_8960,
141 	MSM_HDMI_PHY_8x74,
142 	MSM_HDMI_PHY_8996,
143 	MSM_HDMI_PHY_MAX,
144 };
145 
146 struct hdmi_phy_cfg {
147 	enum hdmi_phy_type type;
148 	void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
149 	void (*powerdown)(struct hdmi_phy *phy);
150 	const char * const *reg_names;
151 	int num_regs;
152 	const char * const *clk_names;
153 	int num_clks;
154 };
155 
156 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
157 extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
158 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
159 extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
160 
161 struct hdmi_phy {
162 	struct platform_device *pdev;
163 	void __iomem *mmio;
164 	struct hdmi_phy_cfg *cfg;
165 	const struct hdmi_phy_funcs *funcs;
166 	struct regulator_bulk_data *regs;
167 	struct clk **clks;
168 };
169 
hdmi_phy_write(struct hdmi_phy * phy,u32 reg,u32 data)170 static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
171 {
172 	msm_writel(data, phy->mmio + reg);
173 }
174 
hdmi_phy_read(struct hdmi_phy * phy,u32 reg)175 static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
176 {
177 	return msm_readl(phy->mmio + reg);
178 }
179 
180 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
181 void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
182 void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
183 void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
184 void __init msm_hdmi_phy_driver_register(void);
185 void __exit msm_hdmi_phy_driver_unregister(void);
186 
187 #ifdef CONFIG_COMMON_CLK
188 int msm_hdmi_pll_8960_init(struct platform_device *pdev);
189 int msm_hdmi_pll_8996_init(struct platform_device *pdev);
190 #else
msm_hdmi_pll_8960_init(struct platform_device * pdev)191 static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
192 {
193 	return -ENODEV;
194 }
195 
msm_hdmi_pll_8996_init(struct platform_device * pdev)196 static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
197 {
198 	return -ENODEV;
199 }
200 #endif
201 
202 /*
203  * audio:
204  */
205 /* Supported HDMI Audio channels and rates */
206 #define	MSM_HDMI_AUDIO_CHANNEL_2	0
207 #define	MSM_HDMI_AUDIO_CHANNEL_4	1
208 #define	MSM_HDMI_AUDIO_CHANNEL_6	2
209 #define	MSM_HDMI_AUDIO_CHANNEL_8	3
210 
211 #define	HDMI_SAMPLE_RATE_32KHZ		0
212 #define	HDMI_SAMPLE_RATE_44_1KHZ	1
213 #define	HDMI_SAMPLE_RATE_48KHZ		2
214 #define	HDMI_SAMPLE_RATE_88_2KHZ	3
215 #define	HDMI_SAMPLE_RATE_96KHZ		4
216 #define	HDMI_SAMPLE_RATE_176_4KHZ	5
217 #define	HDMI_SAMPLE_RATE_192KHZ		6
218 
219 int msm_hdmi_audio_update(struct hdmi *hdmi);
220 int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
221 	uint32_t num_of_channels, uint32_t channel_allocation,
222 	uint32_t level_shift, bool down_mix);
223 void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
224 
225 
226 /*
227  * hdmi bridge:
228  */
229 
230 struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
231 void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
232 
233 /*
234  * hdmi connector:
235  */
236 
237 void msm_hdmi_connector_irq(struct drm_connector *connector);
238 struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
239 int msm_hdmi_hpd_enable(struct drm_connector *connector);
240 
241 /*
242  * i2c adapter for ddc:
243  */
244 
245 void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
246 void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
247 struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
248 
249 /*
250  * hdcp
251  */
252 #ifdef CONFIG_DRM_MSM_HDMI_HDCP
253 struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
254 void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
255 void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
256 void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
257 void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
258 #else
msm_hdmi_hdcp_init(struct hdmi * hdmi)259 static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
260 {
261 	return ERR_PTR(-ENXIO);
262 }
msm_hdmi_hdcp_destroy(struct hdmi * hdmi)263 static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl * hdcp_ctrl)264 static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl * hdcp_ctrl)265 static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl * hdcp_ctrl)266 static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
267 #endif
268 
269 #endif /* __HDMI_CONNECTOR_H__ */
270