1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <config.h>
17
18 #include <dm/device.h>
19 #include <linux/bitops.h>
20 #include <linux/compat.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24 #include <asm/cache.h>
25
26 struct mtd_info;
27 struct nand_chip;
28 struct nand_flash_dev;
29 struct device_node;
30
31 /* Get the flash and manufacturer id and lookup if the type is supported. */
32 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
33 struct nand_chip *chip,
34 int *maf_id, int *dev_id,
35 struct nand_flash_dev *type);
36
37 /* Scan and identify a NAND device */
38 int nand_scan(struct mtd_info *mtd, int max_chips);
39 /*
40 * Separate phases of nand_scan(), allowing board driver to intervene
41 * and override command or ECC setup according to flash type.
42 */
43 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
44 struct nand_flash_dev *table);
45 int nand_scan_tail(struct mtd_info *mtd);
46
47 /* Free resources held by the NAND device */
48 void nand_release(struct mtd_info *mtd);
49
50 /* Internal helper for board drivers which need to override command function */
51 void nand_wait_ready(struct mtd_info *mtd);
52
53 /*
54 * This constant declares the max. oobsize / page, which
55 * is supported now. If you add a chip with bigger oobsize/page
56 * adjust this accordingly.
57 */
58 #define NAND_MAX_OOBSIZE 1664
59 #define NAND_MAX_PAGESIZE 16384
60
61 /*
62 * Constants for hardware specific CLE/ALE/NCE function
63 *
64 * These are bits which can be or'ed to set/clear multiple
65 * bits in one go.
66 */
67 /* Select the chip by setting nCE to low */
68 #define NAND_NCE 0x01
69 /* Select the command latch by setting CLE to high */
70 #define NAND_CLE 0x02
71 /* Select the address latch by setting ALE to high */
72 #define NAND_ALE 0x04
73
74 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
75 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
76 #define NAND_CTRL_CHANGE 0x80
77
78 /*
79 * Standard NAND flash commands
80 */
81 #define NAND_CMD_READ0 0
82 #define NAND_CMD_READ1 1
83 #define NAND_CMD_RNDOUT 5
84 #define NAND_CMD_PAGEPROG 0x10
85 #define NAND_CMD_READOOB 0x50
86 #define NAND_CMD_ERASE1 0x60
87 #define NAND_CMD_STATUS 0x70
88 #define NAND_CMD_SEQIN 0x80
89 #define NAND_CMD_RNDIN 0x85
90 #define NAND_CMD_READID 0x90
91 #define NAND_CMD_ERASE2 0xd0
92 #define NAND_CMD_PARAM 0xec
93 #define NAND_CMD_GET_FEATURES 0xee
94 #define NAND_CMD_SET_FEATURES 0xef
95 #define NAND_CMD_RESET 0xff
96
97 #define NAND_CMD_LOCK 0x2a
98 #define NAND_CMD_UNLOCK1 0x23
99 #define NAND_CMD_UNLOCK2 0x24
100
101 /* Extended commands for large page devices */
102 #define NAND_CMD_READSTART 0x30
103 #define NAND_CMD_RNDOUTSTART 0xE0
104 #define NAND_CMD_CACHEDPROG 0x15
105
106 /* Extended commands for AG-AND device */
107 /*
108 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
109 * there is no way to distinguish that from NAND_CMD_READ0
110 * until the remaining sequence of commands has been completed
111 * so add a high order bit and mask it off in the command.
112 */
113 #define NAND_CMD_DEPLETE1 0x100
114 #define NAND_CMD_DEPLETE2 0x38
115 #define NAND_CMD_STATUS_MULTI 0x71
116 #define NAND_CMD_STATUS_ERROR 0x72
117 /* multi-bank error status (banks 0-3) */
118 #define NAND_CMD_STATUS_ERROR0 0x73
119 #define NAND_CMD_STATUS_ERROR1 0x74
120 #define NAND_CMD_STATUS_ERROR2 0x75
121 #define NAND_CMD_STATUS_ERROR3 0x76
122 #define NAND_CMD_STATUS_RESET 0x7f
123 #define NAND_CMD_STATUS_CLEAR 0xff
124
125 #define NAND_CMD_NONE -1
126
127 /* Status bits */
128 #define NAND_STATUS_FAIL 0x01
129 #define NAND_STATUS_FAIL_N1 0x02
130 #define NAND_STATUS_TRUE_READY 0x20
131 #define NAND_STATUS_READY 0x40
132 #define NAND_STATUS_WP 0x80
133
134 #define NAND_DATA_IFACE_CHECK_ONLY -1
135
136 /*
137 * Constants for ECC_MODES
138 */
139 typedef enum {
140 NAND_ECC_NONE,
141 NAND_ECC_SOFT,
142 NAND_ECC_HW,
143 NAND_ECC_HW_SYNDROME,
144 NAND_ECC_HW_OOB_FIRST,
145 NAND_ECC_SOFT_BCH,
146 } nand_ecc_modes_t;
147
148 enum nand_ecc_algo {
149 NAND_ECC_UNKNOWN,
150 NAND_ECC_HAMMING,
151 NAND_ECC_BCH,
152 };
153
154 /*
155 * Constants for Hardware ECC
156 */
157 /* Reset Hardware ECC for read */
158 #define NAND_ECC_READ 0
159 /* Reset Hardware ECC for write */
160 #define NAND_ECC_WRITE 1
161 /* Enable Hardware ECC before syndrome is read back from flash */
162 #define NAND_ECC_READSYN 2
163
164 /*
165 * Enable generic NAND 'page erased' check. This check is only done when
166 * ecc.correct() returns -EBADMSG.
167 * Set this flag if your implementation does not fix bitflips in erased
168 * pages and you want to rely on the default implementation.
169 */
170 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
171 #define NAND_ECC_MAXIMIZE BIT(1)
172 /*
173 * If your controller already sends the required NAND commands when
174 * reading or writing a page, then the framework is not supposed to
175 * send READ0 and SEQIN/PAGEPROG respectively.
176 */
177 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
178
179 /* Bit mask for flags passed to do_nand_read_ecc */
180 #define NAND_GET_DEVICE 0x80
181
182
183 /*
184 * Option constants for bizarre disfunctionality and real
185 * features.
186 */
187 /* Buswidth is 16 bit */
188 #define NAND_BUSWIDTH_16 0x00000002
189 /* Device supports partial programming without padding */
190 #define NAND_NO_PADDING 0x00000004
191 /* Chip has cache program function */
192 #define NAND_CACHEPRG 0x00000008
193 /* Chip has copy back function */
194 #define NAND_COPYBACK 0x00000010
195 /*
196 * Chip requires ready check on read (for auto-incremented sequential read).
197 * True only for small page devices; large page devices do not support
198 * autoincrement.
199 */
200 #define NAND_NEED_READRDY 0x00000100
201
202 /* Chip does not allow subpage writes */
203 #define NAND_NO_SUBPAGE_WRITE 0x00000200
204
205 /* Device is one of 'new' xD cards that expose fake nand command set */
206 #define NAND_BROKEN_XD 0x00000400
207
208 /* Device behaves just like nand, but is readonly */
209 #define NAND_ROM 0x00000800
210
211 /* Device supports subpage reads */
212 #define NAND_SUBPAGE_READ 0x00001000
213
214 /*
215 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
216 * patterns.
217 */
218 #define NAND_NEED_SCRAMBLING 0x00002000
219
220 /* Device needs 3rd row address cycle */
221 #define NAND_ROW_ADDR_3 0x00004000
222
223 /* Options valid for Samsung large page devices */
224 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
225
226 /* Macros to identify the above */
227 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
228 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
229 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
230
231 /* Non chip related options */
232 /* This option skips the bbt scan during initialization. */
233 #define NAND_SKIP_BBTSCAN 0x00010000
234 /*
235 * This option is defined if the board driver allocates its own buffers
236 * (e.g. because it needs them DMA-coherent).
237 */
238 #define NAND_OWN_BUFFERS 0x00020000
239 /* Chip may not exist, so silence any errors in scan */
240 #define NAND_SCAN_SILENT_NODEV 0x00040000
241 /*
242 * Autodetect nand buswidth with readid/onfi.
243 * This suppose the driver will configure the hardware in 8 bits mode
244 * when calling nand_scan_ident, and update its configuration
245 * before calling nand_scan_tail.
246 */
247 #define NAND_BUSWIDTH_AUTO 0x00080000
248 /*
249 * This option could be defined by controller drivers to protect against
250 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
251 */
252 #define NAND_USE_BOUNCE_BUFFER 0x00100000
253
254 /* Options set by nand scan */
255 /* bbt has already been read */
256 #define NAND_BBT_SCANNED 0x40000000
257 /* Nand scan has allocated controller struct */
258 #define NAND_CONTROLLER_ALLOC 0x80000000
259
260 /* Cell info constants */
261 #define NAND_CI_CHIPNR_MSK 0x03
262 #define NAND_CI_CELLTYPE_MSK 0x0C
263 #define NAND_CI_CELLTYPE_SHIFT 2
264
265 /* ONFI features */
266 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
267 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
268
269 /* ONFI timing mode, used in both asynchronous and synchronous mode */
270 #define ONFI_TIMING_MODE_0 (1 << 0)
271 #define ONFI_TIMING_MODE_1 (1 << 1)
272 #define ONFI_TIMING_MODE_2 (1 << 2)
273 #define ONFI_TIMING_MODE_3 (1 << 3)
274 #define ONFI_TIMING_MODE_4 (1 << 4)
275 #define ONFI_TIMING_MODE_5 (1 << 5)
276 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
277
278 /* ONFI feature address */
279 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
280
281 /* Vendor-specific feature address (Micron) */
282 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
283
284 /* ONFI subfeature parameters length */
285 #define ONFI_SUBFEATURE_PARAM_LEN 4
286
287 /* ONFI optional commands SET/GET FEATURES supported? */
288 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
289
290 struct nand_onfi_params {
291 /* rev info and features block */
292 /* 'O' 'N' 'F' 'I' */
293 u8 sig[4];
294 __le16 revision;
295 __le16 features;
296 __le16 opt_cmd;
297 u8 reserved0[2];
298 __le16 ext_param_page_length; /* since ONFI 2.1 */
299 u8 num_of_param_pages; /* since ONFI 2.1 */
300 u8 reserved1[17];
301
302 /* manufacturer information block */
303 char manufacturer[12];
304 char model[20];
305 u8 jedec_id;
306 __le16 date_code;
307 u8 reserved2[13];
308
309 /* memory organization block */
310 __le32 byte_per_page;
311 __le16 spare_bytes_per_page;
312 __le32 data_bytes_per_ppage;
313 __le16 spare_bytes_per_ppage;
314 __le32 pages_per_block;
315 __le32 blocks_per_lun;
316 u8 lun_count;
317 u8 addr_cycles;
318 u8 bits_per_cell;
319 __le16 bb_per_lun;
320 __le16 block_endurance;
321 u8 guaranteed_good_blocks;
322 __le16 guaranteed_block_endurance;
323 u8 programs_per_page;
324 u8 ppage_attr;
325 u8 ecc_bits;
326 u8 interleaved_bits;
327 u8 interleaved_ops;
328 u8 reserved3[13];
329
330 /* electrical parameter block */
331 u8 io_pin_capacitance_max;
332 __le16 async_timing_mode;
333 __le16 program_cache_timing_mode;
334 __le16 t_prog;
335 __le16 t_bers;
336 __le16 t_r;
337 __le16 t_ccs;
338 __le16 src_sync_timing_mode;
339 u8 src_ssync_features;
340 __le16 clk_pin_capacitance_typ;
341 __le16 io_pin_capacitance_typ;
342 __le16 input_pin_capacitance_typ;
343 u8 input_pin_capacitance_max;
344 u8 driver_strength_support;
345 __le16 t_int_r;
346 __le16 t_adl;
347 u8 reserved4[8];
348
349 /* vendor */
350 __le16 vendor_revision;
351 u8 vendor[88];
352
353 __le16 crc;
354 } __packed;
355
356 #define ONFI_CRC_BASE 0x4F4E
357
358 /* Extended ECC information Block Definition (since ONFI 2.1) */
359 struct onfi_ext_ecc_info {
360 u8 ecc_bits;
361 u8 codeword_size;
362 __le16 bb_per_lun;
363 __le16 block_endurance;
364 u8 reserved[2];
365 } __packed;
366
367 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
368 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
369 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
370 struct onfi_ext_section {
371 u8 type;
372 u8 length;
373 } __packed;
374
375 #define ONFI_EXT_SECTION_MAX 8
376
377 /* Extended Parameter Page Definition (since ONFI 2.1) */
378 struct onfi_ext_param_page {
379 __le16 crc;
380 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
381 u8 reserved0[10];
382 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
383
384 /*
385 * The actual size of the Extended Parameter Page is in
386 * @ext_param_page_length of nand_onfi_params{}.
387 * The following are the variable length sections.
388 * So we do not add any fields below. Please see the ONFI spec.
389 */
390 } __packed;
391
392 struct nand_onfi_vendor_micron {
393 u8 two_plane_read;
394 u8 read_cache;
395 u8 read_unique_id;
396 u8 dq_imped;
397 u8 dq_imped_num_settings;
398 u8 dq_imped_feat_addr;
399 u8 rb_pulldown_strength;
400 u8 rb_pulldown_strength_feat_addr;
401 u8 rb_pulldown_strength_num_settings;
402 u8 otp_mode;
403 u8 otp_page_start;
404 u8 otp_data_prot_addr;
405 u8 otp_num_pages;
406 u8 otp_feat_addr;
407 u8 read_retry_options;
408 u8 reserved[72];
409 u8 param_revision;
410 } __packed;
411
412 struct jedec_ecc_info {
413 u8 ecc_bits;
414 u8 codeword_size;
415 __le16 bb_per_lun;
416 __le16 block_endurance;
417 u8 reserved[2];
418 } __packed;
419
420 /* JEDEC features */
421 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
422
423 struct nand_jedec_params {
424 /* rev info and features block */
425 /* 'J' 'E' 'S' 'D' */
426 u8 sig[4];
427 __le16 revision;
428 __le16 features;
429 u8 opt_cmd[3];
430 __le16 sec_cmd;
431 u8 num_of_param_pages;
432 u8 reserved0[18];
433
434 /* manufacturer information block */
435 char manufacturer[12];
436 char model[20];
437 u8 jedec_id[6];
438 u8 reserved1[10];
439
440 /* memory organization block */
441 __le32 byte_per_page;
442 __le16 spare_bytes_per_page;
443 u8 reserved2[6];
444 __le32 pages_per_block;
445 __le32 blocks_per_lun;
446 u8 lun_count;
447 u8 addr_cycles;
448 u8 bits_per_cell;
449 u8 programs_per_page;
450 u8 multi_plane_addr;
451 u8 multi_plane_op_attr;
452 u8 reserved3[38];
453
454 /* electrical parameter block */
455 __le16 async_sdr_speed_grade;
456 __le16 toggle_ddr_speed_grade;
457 __le16 sync_ddr_speed_grade;
458 u8 async_sdr_features;
459 u8 toggle_ddr_features;
460 u8 sync_ddr_features;
461 __le16 t_prog;
462 __le16 t_bers;
463 __le16 t_r;
464 __le16 t_r_multi_plane;
465 __le16 t_ccs;
466 __le16 io_pin_capacitance_typ;
467 __le16 input_pin_capacitance_typ;
468 __le16 clk_pin_capacitance_typ;
469 u8 driver_strength_support;
470 __le16 t_adl;
471 u8 reserved4[36];
472
473 /* ECC and endurance block */
474 u8 guaranteed_good_blocks;
475 __le16 guaranteed_block_endurance;
476 struct jedec_ecc_info ecc_info[4];
477 u8 reserved5[29];
478
479 /* reserved */
480 u8 reserved6[148];
481
482 /* vendor */
483 __le16 vendor_rev_num;
484 u8 reserved7[88];
485
486 /* CRC for Parameter Page */
487 __le16 crc;
488 } __packed;
489
490 /**
491 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
492 * @lock: protection lock
493 * @active: the mtd device which holds the controller currently
494 * @wq: wait queue to sleep on if a NAND operation is in
495 * progress used instead of the per chip wait queue
496 * when a hw controller is available.
497 */
498 struct nand_hw_control {
499 spinlock_t lock;
500 struct nand_chip *active;
501 };
502
nand_hw_control_init(struct nand_hw_control * nfc)503 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
504 {
505 nfc->active = NULL;
506 spin_lock_init(&nfc->lock);
507 init_waitqueue_head(&nfc->wq);
508 }
509
510 /**
511 * struct nand_ecc_step_info - ECC step information of ECC engine
512 * @stepsize: data bytes per ECC step
513 * @strengths: array of supported strengths
514 * @nstrengths: number of supported strengths
515 */
516 struct nand_ecc_step_info {
517 int stepsize;
518 const int *strengths;
519 int nstrengths;
520 };
521
522 /**
523 * struct nand_ecc_caps - capability of ECC engine
524 * @stepinfos: array of ECC step information
525 * @nstepinfos: number of ECC step information
526 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
527 */
528 struct nand_ecc_caps {
529 const struct nand_ecc_step_info *stepinfos;
530 int nstepinfos;
531 int (*calc_ecc_bytes)(int step_size, int strength);
532 };
533
534 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
535 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
536 static const int __name##_strengths[] = { __VA_ARGS__ }; \
537 static const struct nand_ecc_step_info __name##_stepinfo = { \
538 .stepsize = __step, \
539 .strengths = __name##_strengths, \
540 .nstrengths = ARRAY_SIZE(__name##_strengths), \
541 }; \
542 static const struct nand_ecc_caps __name = { \
543 .stepinfos = &__name##_stepinfo, \
544 .nstepinfos = 1, \
545 .calc_ecc_bytes = __calc, \
546 }
547
548 /**
549 * struct nand_ecc_ctrl - Control structure for ECC
550 * @mode: ECC mode
551 * @algo: ECC algorithm
552 * @steps: number of ECC steps per page
553 * @size: data bytes per ECC step
554 * @bytes: ECC bytes per step
555 * @strength: max number of correctible bits per ECC step
556 * @total: total number of ECC bytes per page
557 * @prepad: padding information for syndrome based ECC generators
558 * @postpad: padding information for syndrome based ECC generators
559 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
560 * @layout: ECC layout control struct pointer
561 * @priv: pointer to private ECC control data
562 * @hwctl: function to control hardware ECC generator. Must only
563 * be provided if an hardware ECC is available
564 * @calculate: function for ECC calculation or readback from ECC hardware
565 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
566 * Should return a positive number representing the number of
567 * corrected bitflips, -EBADMSG if the number of bitflips exceed
568 * ECC strength, or any other error code if the error is not
569 * directly related to correction.
570 * If -EBADMSG is returned the input buffers should be left
571 * untouched.
572 * @read_page_raw: function to read a raw page without ECC. This function
573 * should hide the specific layout used by the ECC
574 * controller and always return contiguous in-band and
575 * out-of-band data even if they're not stored
576 * contiguously on the NAND chip (e.g.
577 * NAND_ECC_HW_SYNDROME interleaves in-band and
578 * out-of-band data).
579 * @write_page_raw: function to write a raw page without ECC. This function
580 * should hide the specific layout used by the ECC
581 * controller and consider the passed data as contiguous
582 * in-band and out-of-band data. ECC controller is
583 * responsible for doing the appropriate transformations
584 * to adapt to its specific layout (e.g.
585 * NAND_ECC_HW_SYNDROME interleaves in-band and
586 * out-of-band data).
587 * @read_page: function to read a page according to the ECC generator
588 * requirements; returns maximum number of bitflips corrected in
589 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
590 * @read_subpage: function to read parts of the page covered by ECC;
591 * returns same as read_page()
592 * @write_subpage: function to write parts of the page covered by ECC.
593 * @write_page: function to write a page according to the ECC generator
594 * requirements.
595 * @write_oob_raw: function to write chip OOB data without ECC
596 * @read_oob_raw: function to read chip OOB data without ECC
597 * @read_oob: function to read chip OOB data
598 * @write_oob: function to write chip OOB data
599 */
600 struct nand_ecc_ctrl {
601 nand_ecc_modes_t mode;
602 enum nand_ecc_algo algo;
603 int steps;
604 int size;
605 int bytes;
606 int total;
607 int strength;
608 int prepad;
609 int postpad;
610 unsigned int options;
611 struct nand_ecclayout *layout;
612 void *priv;
613 void (*hwctl)(struct mtd_info *mtd, int mode);
614 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
615 uint8_t *ecc_code);
616 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
617 uint8_t *calc_ecc);
618 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
619 uint8_t *buf, int oob_required, int page);
620 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
621 const uint8_t *buf, int oob_required, int page);
622 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
623 uint8_t *buf, int oob_required, int page);
624 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
625 uint32_t offs, uint32_t len, uint8_t *buf, int page);
626 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
627 uint32_t offset, uint32_t data_len,
628 const uint8_t *data_buf, int oob_required, int page);
629 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
630 const uint8_t *buf, int oob_required, int page);
631 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
632 int page);
633 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
634 int page);
635 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
636 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
637 int page);
638 };
639
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)640 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
641 {
642 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
643 }
644
645 /**
646 * struct nand_buffers - buffer structure for read/write
647 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
648 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
649 * @databuf: buffer pointer for data, size is (page size + oobsize).
650 *
651 * Do not change the order of buffers. databuf and oobrbuf must be in
652 * consecutive order.
653 */
654 struct nand_buffers {
655 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
656 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
657 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
658 ARCH_DMA_MINALIGN)];
659 };
660
661 /**
662 * struct nand_sdr_timings - SDR NAND chip timings
663 *
664 * This struct defines the timing requirements of a SDR NAND chip.
665 * These information can be found in every NAND datasheets and the timings
666 * meaning are described in the ONFI specifications:
667 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
668 * Parameters)
669 *
670 * All these timings are expressed in picoseconds.
671 *
672 * @tBERS_max: Block erase time
673 * @tCCS_min: Change column setup time
674 * @tPROG_max: Page program time
675 * @tR_max: Page read time
676 * @tALH_min: ALE hold time
677 * @tADL_min: ALE to data loading time
678 * @tALS_min: ALE setup time
679 * @tAR_min: ALE to RE# delay
680 * @tCEA_max: CE# access time
681 * @tCEH_min: CE# high hold time
682 * @tCH_min: CE# hold time
683 * @tCHZ_max: CE# high to output hi-Z
684 * @tCLH_min: CLE hold time
685 * @tCLR_min: CLE to RE# delay
686 * @tCLS_min: CLE setup time
687 * @tCOH_min: CE# high to output hold
688 * @tCS_min: CE# setup time
689 * @tDH_min: Data hold time
690 * @tDS_min: Data setup time
691 * @tFEAT_max: Busy time for Set Features and Get Features
692 * @tIR_min: Output hi-Z to RE# low
693 * @tITC_max: Interface and Timing Mode Change time
694 * @tRC_min: RE# cycle time
695 * @tREA_max: RE# access time
696 * @tREH_min: RE# high hold time
697 * @tRHOH_min: RE# high to output hold
698 * @tRHW_min: RE# high to WE# low
699 * @tRHZ_max: RE# high to output hi-Z
700 * @tRLOH_min: RE# low to output hold
701 * @tRP_min: RE# pulse width
702 * @tRR_min: Ready to RE# low (data only)
703 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
704 * rising edge of R/B#.
705 * @tWB_max: WE# high to SR[6] low
706 * @tWC_min: WE# cycle time
707 * @tWH_min: WE# high hold time
708 * @tWHR_min: WE# high to RE# low
709 * @tWP_min: WE# pulse width
710 * @tWW_min: WP# transition to WE# low
711 */
712 struct nand_sdr_timings {
713 u64 tBERS_max;
714 u32 tCCS_min;
715 u64 tPROG_max;
716 u64 tR_max;
717 u32 tALH_min;
718 u32 tADL_min;
719 u32 tALS_min;
720 u32 tAR_min;
721 u32 tCEA_max;
722 u32 tCEH_min;
723 u32 tCH_min;
724 u32 tCHZ_max;
725 u32 tCLH_min;
726 u32 tCLR_min;
727 u32 tCLS_min;
728 u32 tCOH_min;
729 u32 tCS_min;
730 u32 tDH_min;
731 u32 tDS_min;
732 u32 tFEAT_max;
733 u32 tIR_min;
734 u32 tITC_max;
735 u32 tRC_min;
736 u32 tREA_max;
737 u32 tREH_min;
738 u32 tRHOH_min;
739 u32 tRHW_min;
740 u32 tRHZ_max;
741 u32 tRLOH_min;
742 u32 tRP_min;
743 u32 tRR_min;
744 u64 tRST_max;
745 u32 tWB_max;
746 u32 tWC_min;
747 u32 tWH_min;
748 u32 tWHR_min;
749 u32 tWP_min;
750 u32 tWW_min;
751 };
752
753 /**
754 * enum nand_data_interface_type - NAND interface timing type
755 * @NAND_SDR_IFACE: Single Data Rate interface
756 */
757 enum nand_data_interface_type {
758 NAND_SDR_IFACE,
759 };
760
761 /**
762 * struct nand_data_interface - NAND interface timing
763 * @type: type of the timing
764 * @timings: The timing, type according to @type
765 */
766 struct nand_data_interface {
767 enum nand_data_interface_type type;
768 union {
769 struct nand_sdr_timings sdr;
770 } timings;
771 };
772
773 /**
774 * nand_get_sdr_timings - get SDR timing from data interface
775 * @conf: The data interface
776 */
777 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)778 nand_get_sdr_timings(const struct nand_data_interface *conf)
779 {
780 if (conf->type != NAND_SDR_IFACE)
781 return ERR_PTR(-EINVAL);
782
783 return &conf->timings.sdr;
784 }
785
786 /**
787 * struct nand_chip - NAND Private Flash Chip Data
788 * @mtd: MTD device registered to the MTD framework
789 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
790 * flash device
791 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
792 * flash device.
793 * @flash_node: [BOARDSPECIFIC] device node describing this instance
794 * @read_byte: [REPLACEABLE] read one byte from the chip
795 * @read_word: [REPLACEABLE] read one word from the chip
796 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
797 * low 8 I/O lines
798 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
799 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
800 * @select_chip: [REPLACEABLE] select chip nr
801 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
802 * @block_markbad: [REPLACEABLE] mark a block bad
803 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
804 * ALE/CLE/nCE. Also used to write command and address
805 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
806 * device ready/busy line. If set to NULL no access to
807 * ready/busy is available and the ready/busy information
808 * is read from the chip status register.
809 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
810 * commands to the chip.
811 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
812 * ready.
813 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
814 * setting the read-retry mode. Mostly needed for MLC NAND.
815 * @ecc: [BOARDSPECIFIC] ECC control structure
816 * @buffers: buffer structure for read/write
817 * @buf_align: minimum buffer alignment required by a platform
818 * @hwcontrol: platform-specific hardware control structure
819 * @erase: [REPLACEABLE] erase function
820 * @scan_bbt: [REPLACEABLE] function to scan bad block table
821 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
822 * data from array to read regs (tR).
823 * @state: [INTERN] the current state of the NAND device
824 * @oob_poi: "poison value buffer," used for laying out OOB data
825 * before writing
826 * @page_shift: [INTERN] number of address bits in a page (column
827 * address bits).
828 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
829 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
830 * @chip_shift: [INTERN] number of address bits in one chip
831 * @options: [BOARDSPECIFIC] various chip options. They can partly
832 * be set to inform nand_scan about special functionality.
833 * See the defines for further explanation.
834 * @bbt_options: [INTERN] bad block specific options. All options used
835 * here must come from bbm.h. By default, these options
836 * will be copied to the appropriate nand_bbt_descr's.
837 * @badblockpos: [INTERN] position of the bad block marker in the oob
838 * area.
839 * @badblockbits: [INTERN] minimum number of set bits in a good block's
840 * bad block marker position; i.e., BBM == 11110111b is
841 * not bad when badblockbits == 7
842 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
843 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
844 * Minimum amount of bit errors per @ecc_step_ds guaranteed
845 * to be correctable. If unknown, set to zero.
846 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
847 * also from the datasheet. It is the recommended ECC step
848 * size, if known; if unknown, set to zero.
849 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
850 * set to the actually used ONFI mode if the chip is
851 * ONFI compliant or deduced from the datasheet if
852 * the NAND chip is not ONFI compliant.
853 * @numchips: [INTERN] number of physical chips
854 * @chipsize: [INTERN] the size of one chip for multichip arrays
855 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
856 * @pagebuf: [INTERN] holds the pagenumber which is currently in
857 * data_buf.
858 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
859 * currently in data_buf.
860 * @subpagesize: [INTERN] holds the subpagesize
861 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
862 * non 0 if ONFI supported.
863 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
864 * non 0 if JEDEC supported.
865 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
866 * supported, 0 otherwise.
867 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
868 * supported, 0 otherwise.
869 * @read_retries: [INTERN] the number of read retry modes supported
870 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
871 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
872 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
873 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
874 * means the configuration should not be applied but
875 * only checked.
876 * @bbt: [INTERN] bad block table pointer
877 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
878 * lookup.
879 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
880 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
881 * bad block scan.
882 * @controller: [REPLACEABLE] a pointer to a hardware controller
883 * structure which is shared among multiple independent
884 * devices.
885 * @priv: [OPTIONAL] pointer to private chip data
886 * @write_page: [REPLACEABLE] High-level page write function
887 */
888
889 struct nand_chip {
890 struct mtd_info mtd;
891 void __iomem *IO_ADDR_R;
892 void __iomem *IO_ADDR_W;
893
894 int flash_node;
895
896 uint8_t (*read_byte)(struct mtd_info *mtd);
897 u16 (*read_word)(struct mtd_info *mtd);
898 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
899 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
900 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
901 void (*select_chip)(struct mtd_info *mtd, int chip);
902 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
903 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
904 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
905 int (*dev_ready)(struct mtd_info *mtd);
906 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
907 int page_addr);
908 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
909 int (*erase)(struct mtd_info *mtd, int page);
910 int (*scan_bbt)(struct mtd_info *mtd);
911 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
912 uint32_t offset, int data_len, const uint8_t *buf,
913 int oob_required, int page, int raw);
914 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
915 int feature_addr, uint8_t *subfeature_para);
916 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
917 int feature_addr, uint8_t *subfeature_para);
918 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
919 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
920 const struct nand_data_interface *conf);
921
922
923 int chip_delay;
924 unsigned int options;
925 unsigned int bbt_options;
926
927 int page_shift;
928 int phys_erase_shift;
929 int bbt_erase_shift;
930 int chip_shift;
931 int numchips;
932 uint64_t chipsize;
933 int pagemask;
934 int pagebuf;
935 unsigned int pagebuf_bitflips;
936 int subpagesize;
937 uint8_t bits_per_cell;
938 uint16_t ecc_strength_ds;
939 uint16_t ecc_step_ds;
940 int onfi_timing_mode_default;
941 int badblockpos;
942 int badblockbits;
943
944 int onfi_version;
945 int jedec_version;
946 struct nand_onfi_params onfi_params;
947 struct nand_jedec_params jedec_params;
948
949 struct nand_data_interface *data_interface;
950
951 int read_retries;
952
953 flstate_t state;
954
955 uint8_t *oob_poi;
956 struct nand_hw_control *controller;
957 struct nand_ecclayout *ecclayout;
958
959 struct nand_ecc_ctrl ecc;
960 struct nand_buffers *buffers;
961 unsigned long buf_align;
962 struct nand_hw_control hwcontrol;
963
964 uint8_t *bbt;
965 struct nand_bbt_descr *bbt_td;
966 struct nand_bbt_descr *bbt_md;
967
968 struct nand_bbt_descr *badblock_pattern;
969
970 void *priv;
971 };
972
nand_set_flash_node(struct nand_chip * chip,ofnode node)973 static inline void nand_set_flash_node(struct nand_chip *chip,
974 ofnode node)
975 {
976 chip->flash_node = ofnode_to_offset(node);
977 }
978
nand_get_flash_node(struct nand_chip * chip)979 static inline ofnode nand_get_flash_node(struct nand_chip *chip)
980 {
981 return offset_to_ofnode(chip->flash_node);
982 }
983
mtd_to_nand(struct mtd_info * mtd)984 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
985 {
986 return container_of(mtd, struct nand_chip, mtd);
987 }
988
nand_to_mtd(struct nand_chip * chip)989 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
990 {
991 return &chip->mtd;
992 }
993
nand_get_controller_data(struct nand_chip * chip)994 static inline void *nand_get_controller_data(struct nand_chip *chip)
995 {
996 return chip->priv;
997 }
998
nand_set_controller_data(struct nand_chip * chip,void * priv)999 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1000 {
1001 chip->priv = priv;
1002 }
1003
1004 /*
1005 * NAND Flash Manufacturer ID Codes
1006 */
1007 #define NAND_MFR_TOSHIBA 0x98
1008 #define NAND_MFR_SAMSUNG 0xec
1009 #define NAND_MFR_FUJITSU 0x04
1010 #define NAND_MFR_NATIONAL 0x8f
1011 #define NAND_MFR_RENESAS 0x07
1012 #define NAND_MFR_STMICRO 0x20
1013 #define NAND_MFR_HYNIX 0xad
1014 #define NAND_MFR_MICRON 0x2c
1015 #define NAND_MFR_AMD 0x01
1016 #define NAND_MFR_MACRONIX 0xc2
1017 #define NAND_MFR_EON 0x92
1018 #define NAND_MFR_SANDISK 0x45
1019 #define NAND_MFR_INTEL 0x89
1020 #define NAND_MFR_ATO 0x9b
1021
1022 /* The maximum expected count of bytes in the NAND ID sequence */
1023 #define NAND_MAX_ID_LEN 8
1024
1025 /*
1026 * A helper for defining older NAND chips where the second ID byte fully
1027 * defined the chip, including the geometry (chip size, eraseblock size, page
1028 * size). All these chips have 512 bytes NAND page size.
1029 */
1030 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1031 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1032 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1033
1034 /*
1035 * A helper for defining newer chips which report their page size and
1036 * eraseblock size via the extended ID bytes.
1037 *
1038 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1039 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1040 * device ID now only represented a particular total chip size (and voltage,
1041 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1042 * using the same device ID.
1043 */
1044 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1045 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1046 .options = (opts) }
1047
1048 #define NAND_ECC_INFO(_strength, _step) \
1049 { .strength_ds = (_strength), .step_ds = (_step) }
1050 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1051 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1052
1053 /**
1054 * struct nand_flash_dev - NAND Flash Device ID Structure
1055 * @name: a human-readable name of the NAND chip
1056 * @dev_id: the device ID (the second byte of the full chip ID array)
1057 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1058 * memory address as @id[0])
1059 * @dev_id: device ID part of the full chip ID array (refers the same memory
1060 * address as @id[1])
1061 * @id: full device ID array
1062 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1063 * well as the eraseblock size) is determined from the extended NAND
1064 * chip ID array)
1065 * @chipsize: total chip size in MiB
1066 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1067 * @options: stores various chip bit options
1068 * @id_len: The valid length of the @id.
1069 * @oobsize: OOB size
1070 * @ecc: ECC correctability and step information from the datasheet.
1071 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1072 * @ecc_strength_ds in nand_chip{}.
1073 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1074 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1075 * For example, the "4bit ECC for each 512Byte" can be set with
1076 * NAND_ECC_INFO(4, 512).
1077 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1078 * reset. Should be deduced from timings described
1079 * in the datasheet.
1080 *
1081 */
1082 struct nand_flash_dev {
1083 char *name;
1084 union {
1085 struct {
1086 uint8_t mfr_id;
1087 uint8_t dev_id;
1088 };
1089 uint8_t id[NAND_MAX_ID_LEN];
1090 };
1091 unsigned int pagesize;
1092 unsigned int chipsize;
1093 unsigned int erasesize;
1094 unsigned int options;
1095 uint16_t id_len;
1096 uint16_t oobsize;
1097 struct {
1098 uint16_t strength_ds;
1099 uint16_t step_ds;
1100 } ecc;
1101 int onfi_timing_mode_default;
1102 };
1103
1104 /**
1105 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1106 * @name: Manufacturer name
1107 * @id: manufacturer ID code of device.
1108 */
1109 struct nand_manufacturers {
1110 int id;
1111 char *name;
1112 };
1113
1114 extern struct nand_flash_dev nand_flash_ids[];
1115 extern struct nand_manufacturers nand_manuf_ids[];
1116
1117 int nand_default_bbt(struct mtd_info *mtd);
1118 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1119 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1120 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1121 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1122 int allowbbt);
1123 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1124 size_t *retlen, uint8_t *buf);
1125
1126 /*
1127 * Constants for oob configuration
1128 */
1129 #define NAND_SMALL_BADBLOCK_POS 5
1130 #define NAND_LARGE_BADBLOCK_POS 0
1131
1132 /**
1133 * struct platform_nand_chip - chip level device structure
1134 * @nr_chips: max. number of chips to scan for
1135 * @chip_offset: chip number offset
1136 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1137 * @partitions: mtd partition list
1138 * @chip_delay: R/B delay value in us
1139 * @options: Option flags, e.g. 16bit buswidth
1140 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1141 * @part_probe_types: NULL-terminated array of probe types
1142 */
1143 struct platform_nand_chip {
1144 int nr_chips;
1145 int chip_offset;
1146 int nr_partitions;
1147 struct mtd_partition *partitions;
1148 int chip_delay;
1149 unsigned int options;
1150 unsigned int bbt_options;
1151 const char **part_probe_types;
1152 };
1153
1154 /* Keep gcc happy */
1155 struct platform_device;
1156
1157 /**
1158 * struct platform_nand_ctrl - controller level device structure
1159 * @probe: platform specific function to probe/setup hardware
1160 * @remove: platform specific function to remove/teardown hardware
1161 * @hwcontrol: platform specific hardware control structure
1162 * @dev_ready: platform specific function to read ready/busy pin
1163 * @select_chip: platform specific chip select function
1164 * @cmd_ctrl: platform specific function for controlling
1165 * ALE/CLE/nCE. Also used to write command and address
1166 * @write_buf: platform specific function for write buffer
1167 * @read_buf: platform specific function for read buffer
1168 * @read_byte: platform specific function to read one byte from chip
1169 * @priv: private data to transport driver specific settings
1170 *
1171 * All fields are optional and depend on the hardware driver requirements
1172 */
1173 struct platform_nand_ctrl {
1174 int (*probe)(struct platform_device *pdev);
1175 void (*remove)(struct platform_device *pdev);
1176 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1177 int (*dev_ready)(struct mtd_info *mtd);
1178 void (*select_chip)(struct mtd_info *mtd, int chip);
1179 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1180 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1181 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1182 unsigned char (*read_byte)(struct mtd_info *mtd);
1183 void *priv;
1184 };
1185
1186 /**
1187 * struct platform_nand_data - container structure for platform-specific data
1188 * @chip: chip level chip structure
1189 * @ctrl: controller level device structure
1190 */
1191 struct platform_nand_data {
1192 struct platform_nand_chip chip;
1193 struct platform_nand_ctrl ctrl;
1194 };
1195
1196 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1197 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1198 static inline int onfi_feature(struct nand_chip *chip)
1199 {
1200 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1201 }
1202
1203 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1204 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1205 {
1206 if (!chip->onfi_version)
1207 return ONFI_TIMING_MODE_UNKNOWN;
1208 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1209 }
1210
1211 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1212 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1213 {
1214 if (!chip->onfi_version)
1215 return ONFI_TIMING_MODE_UNKNOWN;
1216 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1217 }
1218 #else
onfi_feature(struct nand_chip * chip)1219 static inline int onfi_feature(struct nand_chip *chip)
1220 {
1221 return 0;
1222 }
1223
onfi_get_async_timing_mode(struct nand_chip * chip)1224 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1225 {
1226 return ONFI_TIMING_MODE_UNKNOWN;
1227 }
1228
onfi_get_sync_timing_mode(struct nand_chip * chip)1229 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1230 {
1231 return ONFI_TIMING_MODE_UNKNOWN;
1232 }
1233 #endif
1234
1235 int onfi_init_data_interface(struct nand_chip *chip,
1236 struct nand_data_interface *iface,
1237 enum nand_data_interface_type type,
1238 int timing_mode);
1239
1240 /*
1241 * Check if it is a SLC nand.
1242 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1243 * We do not distinguish the MLC and TLC now.
1244 */
nand_is_slc(struct nand_chip * chip)1245 static inline bool nand_is_slc(struct nand_chip *chip)
1246 {
1247 return chip->bits_per_cell == 1;
1248 }
1249
1250 /**
1251 * Check if the opcode's address should be sent only on the lower 8 bits
1252 * @command: opcode to check
1253 */
nand_opcode_8bits(unsigned int command)1254 static inline int nand_opcode_8bits(unsigned int command)
1255 {
1256 switch (command) {
1257 case NAND_CMD_READID:
1258 case NAND_CMD_PARAM:
1259 case NAND_CMD_GET_FEATURES:
1260 case NAND_CMD_SET_FEATURES:
1261 return 1;
1262 default:
1263 break;
1264 }
1265 return 0;
1266 }
1267
1268 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1269 static inline int jedec_feature(struct nand_chip *chip)
1270 {
1271 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1272 : 0;
1273 }
1274
1275 /* Standard NAND functions from nand_base.c */
1276 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1277 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1278 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1279 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1280 uint8_t nand_read_byte(struct mtd_info *mtd);
1281
1282 /* get timing characteristics from ONFI timing mode. */
1283 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1284 /* get data interface from ONFI timing mode 0, used after reset. */
1285 const struct nand_data_interface *nand_get_default_data_interface(void);
1286
1287 int nand_check_erased_ecc_chunk(void *data, int datalen,
1288 void *ecc, int ecclen,
1289 void *extraoob, int extraooblen,
1290 int threshold);
1291
1292 int nand_check_ecc_caps(struct nand_chip *chip,
1293 const struct nand_ecc_caps *caps, int oobavail);
1294
1295 int nand_match_ecc_req(struct nand_chip *chip,
1296 const struct nand_ecc_caps *caps, int oobavail);
1297
1298 int nand_maximize_ecc(struct nand_chip *chip,
1299 const struct nand_ecc_caps *caps, int oobavail);
1300
1301 /* Reset and initialize a NAND device */
1302 int nand_reset(struct nand_chip *chip, int chipnr);
1303
1304 /* NAND operation helpers */
1305 int nand_reset_op(struct nand_chip *chip);
1306 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1307 unsigned int len);
1308 int nand_status_op(struct nand_chip *chip, u8 *status);
1309 int nand_exit_status_op(struct nand_chip *chip);
1310 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1311 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1312 unsigned int offset_in_page, void *buf, unsigned int len);
1313 int nand_change_read_column_op(struct nand_chip *chip,
1314 unsigned int offset_in_page, void *buf,
1315 unsigned int len, bool force_8bit);
1316 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1317 unsigned int offset_in_page, void *buf, unsigned int len);
1318 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1319 unsigned int offset_in_page, const void *buf,
1320 unsigned int len);
1321 int nand_prog_page_end_op(struct nand_chip *chip);
1322 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1323 unsigned int offset_in_page, const void *buf,
1324 unsigned int len);
1325 int nand_change_write_column_op(struct nand_chip *chip,
1326 unsigned int offset_in_page, const void *buf,
1327 unsigned int len, bool force_8bit);
1328 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1329 bool force_8bit);
1330 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1331 unsigned int len, bool force_8bit);
1332
1333 #endif /* __LINUX_MTD_RAWNAND_H */
1334