| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3308.c | 158 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) in rk3308_i2c_set_clk()
192 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz) in rk3308_mac_set_clk()
322 static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz) in rk3308_saradc_set_clk()
350 static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz) in rk3308_tsadc_set_clk()
393 static ulong rk3308_spi_set_clk(struct clk *clk, uint hz) in rk3308_spi_set_clk()
437 static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz) in rk3308_pwm_set_clk()
490 static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz) in rk3308_vop_set_clk()
572 ulong hz) in rk3308_bus_set_clk()
635 ulong hz) in rk3308_peri_set_clk()
694 ulong hz) in rk3308_audio_set_clk()
[all …]
|
| A D | clk_rv1108.c | 37 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
206 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk()
231 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio1_set_clk()
257 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio0_set_clk()
292 static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_dclk_vop_set_clk()
321 static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_bus_set_clk()
373 static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_peri_set_clk()
389 static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_hclk_peri_set_clk()
404 static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_pclk_peri_set_clk()
452 static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz) in rv1108_i2c_set_clk()
|
| A D | clk_px30.c | 319 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2c_set_clk()
648 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_saradc_set_clk()
674 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_tsadc_set_clk()
869 ulong hz) in px30_bus_set_clk()
935 ulong hz) in px30_peri_set_clk()
993 ulong hz) in px30_crypto_set_clk()
1040 ulong hz) in px30_i2s1_mclk_set_clk()
1057 static ulong px30_mac_set_clk(struct px30_clk_priv *priv, uint hz) in px30_mac_set_clk()
1083 static int px30_mac_set_speed_clk(struct px30_clk_priv *priv, uint hz) in px30_mac_set_speed_clk()
1109 enum px30_pll_id pll_id, ulong hz) in px30_clk_set_pll_rate()
[all …]
|
| A D | clk_rk3128.c | 33 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
371 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk()
406 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) in rk3128_saradc_set_clk()
420 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_vop_set_clk()
|
| A D | clk_rk3188.c | 78 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
125 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr()
171 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu()
|
| A D | clk_rk3328.c | 37 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
365 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) in rk3328_i2c_set_clk()
522 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_pwm_set_clk()
545 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_saradc_set_clk()
569 static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_spi_set_clk()
|
| A D | clk_rk3368.c | 48 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
405 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk()
443 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk()
|
| A D | clk_rk3399.c | 52 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
556 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) in rk3399_i2c_set_clk()
655 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) in rk3399_spi_set_clk()
682 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz) in rk3399_vop_set_clk()
899 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) in rk3399_saradc_set_clk()
1488 uint hz) in rk3399_i2c_set_pmuclk()
|
| A D | clk_rk3288.c | 140 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
183 unsigned int hz) in rkclk_configure_ddr()
736 static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz) in rockchip_saradc_set_clk()
|
| A D | clk_rk3036.c | 36 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
|
| A D | clk_rk322x.c | 34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
|
| /u-boot/drivers/spi/ |
| A D | cadence_qspi.c | 28 static int cadence_spi_write_speed(struct udevice *bus, uint hz) in cadence_spi_write_speed()
55 static int spi_calibration(struct udevice *bus, uint hz) in spi_calibration()
131 static int cadence_spi_set_speed(struct udevice *bus, uint hz) in cadence_spi_set_speed()
|
| A D | kirkwood_spi.c | 110 static int mvebu_spi_set_speed(struct udevice *bus, uint hz) in mvebu_spi_set_speed()
|
| A D | mvebu_a3700_spi.c | 188 static int mvebu_spi_set_speed(struct udevice *bus, uint hz) in mvebu_spi_set_speed()
|
| /u-boot/arch/arm/mach-sunxi/ |
| A D | clock_sun4i.c | 118 void clock_set_pll1(unsigned int hz) in clock_set_pll1()
227 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock()
|
| A D | clock_sun6i.c | 337 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock()
|
| /u-boot/cmd/ |
| A D | bdinfo.c | 45 void bdinfo_print_mhz(const char *name, unsigned long hz) in bdinfo_print_mhz()
|
| /u-boot/lib/bzip2/ |
| A D | bzlib_blocksort.c | 121 #define fpush(lz,hz) { stackLo[sp] = lz; \ argument
125 #define fpop(lz,hz) { sp--; \ argument
637 #define mpush(lz,hz,dz) { stackLo[sp] = lz; \ argument
642 #define mpop(lz,hz,dz) { sp--; \ argument
|
| /u-boot/board/Arcturus/ucp1020/ |
| A D | ucp1020.c | 45 void spi_set_speed(struct spi_slave *slave, uint hz) in spi_set_speed()
|
| /u-boot/drivers/video/ |
| A D | mxsfb.c | 30 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000)) argument
|
| /u-boot/arch/arm/mach-nexell/ |
| A D | timer.c | 168 unsigned long hz = TIMER_HZ; in get_timer() local
|
| /u-boot/drivers/mmc/ |
| A D | gen_atmel_mci.c | 92 static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
|
| A D | sunxi_mmc.c | 102 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) in mmc_set_mod_clk()
|
| /u-boot/drivers/clk/ |
| A D | clk_pic32.c | 121 ulong hz; in pic32_get_sysclk() local
|
| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk3328.c | 76 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll()
|