1 /*
2  * SPDX-License-Identifier: MIT
3  */
4 
5 #include "gem/i915_gem_mman.h"
6 #include "gt/intel_engine_user.h"
7 
8 #include "i915_drv.h"
9 #include "i915_perf.h"
10 
i915_getparam_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)11 int i915_getparam_ioctl(struct drm_device *dev, void *data,
12 			struct drm_file *file_priv)
13 {
14 	struct drm_i915_private *i915 = to_i915(dev);
15 	struct pci_dev *pdev = to_pci_dev(dev->dev);
16 	const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
17 	drm_i915_getparam_t *param = data;
18 	int value = 0;
19 
20 	switch (param->param) {
21 	case I915_PARAM_IRQ_ACTIVE:
22 	case I915_PARAM_ALLOW_BATCHBUFFER:
23 	case I915_PARAM_LAST_DISPATCH:
24 	case I915_PARAM_HAS_EXEC_CONSTANTS:
25 		/* Reject all old ums/dri params. */
26 		return -ENODEV;
27 	case I915_PARAM_CHIPSET_ID:
28 		value = pdev->device;
29 		break;
30 	case I915_PARAM_REVISION:
31 		value = pdev->revision;
32 		break;
33 	case I915_PARAM_NUM_FENCES_AVAIL:
34 		value = i915->ggtt.num_fences;
35 		break;
36 	case I915_PARAM_HAS_OVERLAY:
37 		value = !!i915->overlay;
38 		break;
39 	case I915_PARAM_HAS_BSD:
40 		value = !!intel_engine_lookup_user(i915,
41 						   I915_ENGINE_CLASS_VIDEO, 0);
42 		break;
43 	case I915_PARAM_HAS_BLT:
44 		value = !!intel_engine_lookup_user(i915,
45 						   I915_ENGINE_CLASS_COPY, 0);
46 		break;
47 	case I915_PARAM_HAS_VEBOX:
48 		value = !!intel_engine_lookup_user(i915,
49 						   I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
50 		break;
51 	case I915_PARAM_HAS_BSD2:
52 		value = !!intel_engine_lookup_user(i915,
53 						   I915_ENGINE_CLASS_VIDEO, 1);
54 		break;
55 	case I915_PARAM_HAS_LLC:
56 		value = HAS_LLC(i915);
57 		break;
58 	case I915_PARAM_HAS_WT:
59 		value = HAS_WT(i915);
60 		break;
61 	case I915_PARAM_HAS_ALIASING_PPGTT:
62 		value = INTEL_PPGTT(i915);
63 		break;
64 	case I915_PARAM_HAS_SEMAPHORES:
65 		value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
66 		break;
67 	case I915_PARAM_HAS_SECURE_BATCHES:
68 		value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
69 		break;
70 	case I915_PARAM_CMD_PARSER_VERSION:
71 		value = i915_cmd_parser_get_version(i915);
72 		break;
73 	case I915_PARAM_SUBSLICE_TOTAL:
74 		value = intel_sseu_subslice_total(sseu);
75 		if (!value)
76 			return -ENODEV;
77 		break;
78 	case I915_PARAM_EU_TOTAL:
79 		value = sseu->eu_total;
80 		if (!value)
81 			return -ENODEV;
82 		break;
83 	case I915_PARAM_HAS_GPU_RESET:
84 		value = i915->params.enable_hangcheck &&
85 			intel_has_gpu_reset(&i915->gt);
86 		if (value && intel_has_reset_engine(&i915->gt))
87 			value = 2;
88 		break;
89 	case I915_PARAM_HAS_RESOURCE_STREAMER:
90 		value = 0;
91 		break;
92 	case I915_PARAM_HAS_POOLED_EU:
93 		value = HAS_POOLED_EU(i915);
94 		break;
95 	case I915_PARAM_MIN_EU_IN_POOL:
96 		value = sseu->min_eu_in_pool;
97 		break;
98 	case I915_PARAM_HUC_STATUS:
99 		value = intel_huc_check_status(&i915->gt.uc.huc);
100 		if (value < 0)
101 			return value;
102 		break;
103 	case I915_PARAM_MMAP_GTT_VERSION:
104 		/* Though we've started our numbering from 1, and so class all
105 		 * earlier versions as 0, in effect their value is undefined as
106 		 * the ioctl will report EINVAL for the unknown param!
107 		 */
108 		value = i915_gem_mmap_gtt_version();
109 		break;
110 	case I915_PARAM_HAS_SCHEDULER:
111 		value = i915->caps.scheduler;
112 		break;
113 
114 	case I915_PARAM_MMAP_VERSION:
115 		/* Remember to bump this if the version changes! */
116 	case I915_PARAM_HAS_GEM:
117 	case I915_PARAM_HAS_PAGEFLIPPING:
118 	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
119 	case I915_PARAM_HAS_RELAXED_FENCING:
120 	case I915_PARAM_HAS_COHERENT_RINGS:
121 	case I915_PARAM_HAS_RELAXED_DELTA:
122 	case I915_PARAM_HAS_GEN7_SOL_RESET:
123 	case I915_PARAM_HAS_WAIT_TIMEOUT:
124 	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
125 	case I915_PARAM_HAS_PINNED_BATCHES:
126 	case I915_PARAM_HAS_EXEC_NO_RELOC:
127 	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
128 	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
129 	case I915_PARAM_HAS_EXEC_SOFTPIN:
130 	case I915_PARAM_HAS_EXEC_ASYNC:
131 	case I915_PARAM_HAS_EXEC_FENCE:
132 	case I915_PARAM_HAS_EXEC_CAPTURE:
133 	case I915_PARAM_HAS_EXEC_BATCH_FIRST:
134 	case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
135 	case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
136 	case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
137 	case I915_PARAM_HAS_USERPTR_PROBE:
138 		/* For the time being all of these are always true;
139 		 * if some supported hardware does not have one of these
140 		 * features this value needs to be provided from
141 		 * INTEL_INFO(), a feature macro, or similar.
142 		 */
143 		value = 1;
144 		break;
145 	case I915_PARAM_HAS_CONTEXT_ISOLATION:
146 		value = intel_engines_has_context_isolation(i915);
147 		break;
148 	case I915_PARAM_SLICE_MASK:
149 		value = sseu->slice_mask;
150 		if (!value)
151 			return -ENODEV;
152 		break;
153 	case I915_PARAM_SUBSLICE_MASK:
154 		/* Only copy bits from the first slice */
155 		memcpy(&value, sseu->subslice_mask,
156 		       min(sseu->ss_stride, (u8)sizeof(value)));
157 		if (!value)
158 			return -ENODEV;
159 		break;
160 	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
161 		value = i915->gt.clock_frequency;
162 		break;
163 	case I915_PARAM_MMAP_GTT_COHERENT:
164 		value = INTEL_INFO(i915)->has_coherent_ggtt;
165 		break;
166 	case I915_PARAM_PERF_REVISION:
167 		value = i915_perf_ioctl_version();
168 		break;
169 	default:
170 		DRM_DEBUG("Unknown parameter %d\n", param->param);
171 		return -EINVAL;
172 	}
173 
174 	if (put_user(value, param->value))
175 		return -EFAULT;
176 
177 	return 0;
178 }
179