1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <lib/mmio.h>
8 #include <lib/utils_def.h>
9
10 #include <imx_aips.h>
11 #include <imx_regs.h>
12
imx_aips_set_default_access(struct aipstz_regs * aips_regs)13 static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
14 {
15 int i;
16 uintptr_t addr;
17
18 /*
19 * See section 4.7.7.1 AIPSTZ_MPR field descriptions
20 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
21 * 0111 ->
22 * 0: Write Access from master not buffered
23 * 1: Master is trusted for read access
24 * 1: Master is trsuted for write access
25 * 1: Access from master is not forced to user mode
26 */
27 addr = (uintptr_t)&aips_regs->aipstz_mpr;
28 mmio_write_32(addr, 0x77777777);
29
30 /*
31 * Helpfully the OPACR registers have the logical inversion of the above
32 * See section 4.7.7.1 AIPSTZ_MPR field descriptions
33 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
34 * 0000 ->
35 * 0: Write Access to the peripheral is not buffered by AIPSTZ
36 * 0: The peripheral does not require supervisor priv to access
37 * 0: Master is trsuted for write access
38 * 0: Access from master is not forced to user mode
39 */
40 for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
41 addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
42 mmio_write_32(addr, 0x00000000);
43 }
44 }
45
imx_aips_init(void)46 void imx_aips_init(void)
47 {
48 int i;
49 struct aipstz_regs *aips_regs[] = {
50 (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
51 (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
52 (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
53 };
54
55 for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
56 imx_aips_set_default_access(aips_regs[i]);
57 }
58