1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2017 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <imx.h>
9 #include <io.h>
10 #include <mm/core_memprot.h>
11 #include <platform_config.h>
12 #include <stdint.h>
13
gpc_base(void)14 static vaddr_t gpc_base(void)
15 {
16 return core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, 1);
17 }
18
imx_gpcv2_set_core_pgc(bool enable,uint32_t offset)19 void imx_gpcv2_set_core_pgc(bool enable, uint32_t offset)
20 {
21 uint32_t val = io_read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK);
22
23 if (enable)
24 val |= GPC_PGC_PCG_MASK;
25
26 io_write32(gpc_base() + offset, val);
27 }
28
imx_gpcv2_set_core1_pdn_by_software(void)29 void imx_gpcv2_set_core1_pdn_by_software(void)
30 {
31 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ);
32
33 imx_gpcv2_set_core_pgc(true, GPC_PGC_C1);
34
35 val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK;
36
37 io_write32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ, val);
38
39 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ) &
40 GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK) != 0)
41 ;
42
43 imx_gpcv2_set_core_pgc(false, GPC_PGC_C1);
44 }
45
imx_gpcv2_set_core1_pup_by_software(void)46 void imx_gpcv2_set_core1_pup_by_software(void)
47 {
48 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ);
49
50 imx_gpcv2_set_core_pgc(true, GPC_PGC_C1);
51
52 val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK;
53
54 io_write32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ, val);
55
56 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ) &
57 GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK) != 0)
58 ;
59
60 imx_gpcv2_set_core_pgc(false, GPC_PGC_C1);
61 }
62