1 /*
2 * Routines to indentify caches on Intel CPU.
3 *
4 * Changes:
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
8 */
9
10 #include <xen/init.h>
11 #include <xen/lib.h>
12 #include <xen/errno.h>
13 #include <asm/processor.h>
14
15 #define LVL_1_INST 1
16 #define LVL_1_DATA 2
17 #define LVL_2 3
18 #define LVL_3 4
19 #define LVL_TRACE 5
20
21 struct _cache_table
22 {
23 unsigned char descriptor;
24 char cache_type;
25 short size;
26 };
27
28 /* all the cache descriptor types we care about (no TLB or trace cache entries) */
29 static const struct _cache_table cache_table[] =
30 {
31 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
32 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
33 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
34 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
35 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
36 { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
37 { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
38 { 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
39 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
40 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
41 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
42 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
43 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
44 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
45 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
46 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
47 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
48 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
49 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
50 { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
51 { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
52 { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
53 { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
54 { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
55 { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
56 { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
57 { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
58 { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
59 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
60 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
62 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
63 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
64 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
65 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
66 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
67 { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
68 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
69 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
70 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
71 { 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
72 { 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
73 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
74 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
75 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
76 { 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
77 { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
78 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
79 { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
80 { 0x00, 0, 0}
81 };
82
cpuid4_cache_lookup(int index,struct cpuid4_info * this_leaf)83 int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf)
84 {
85 union _cpuid4_leaf_eax eax;
86 union _cpuid4_leaf_ebx ebx;
87 union _cpuid4_leaf_ecx ecx;
88 unsigned edx;
89
90 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
91 if (eax.split.type == CACHE_TYPE_NULL)
92 return -EIO; /* better error ? */
93
94 this_leaf->eax = eax;
95 this_leaf->ebx = ebx;
96 this_leaf->ecx = ecx;
97 this_leaf->size = (ecx.split.number_of_sets + 1) *
98 (ebx.split.coherency_line_size + 1) *
99 (ebx.split.physical_line_partition + 1) *
100 (ebx.split.ways_of_associativity + 1);
101 return 0;
102 }
103
find_num_cache_leaves(void)104 static int find_num_cache_leaves(void)
105 {
106 unsigned int eax, ebx, ecx, edx;
107 union _cpuid4_leaf_eax cache_eax;
108 int i = -1;
109
110 do {
111 ++i;
112 /* Do cpuid(4) loop to find out num_cache_leaves */
113 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
114 cache_eax.full = eax;
115 } while (cache_eax.split.type != CACHE_TYPE_NULL);
116 return i;
117 }
118
init_intel_cacheinfo(struct cpuinfo_x86 * c)119 void init_intel_cacheinfo(struct cpuinfo_x86 *c)
120 {
121 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
122 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
123 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
124 static unsigned int num_cache_leaves;
125
126 if (c->cpuid_level > 3) {
127 static int is_initialized;
128
129 if (is_initialized == 0) {
130 /* Init num_cache_leaves from boot CPU */
131 num_cache_leaves = find_num_cache_leaves();
132 is_initialized++;
133 }
134
135 /*
136 * Whenever possible use cpuid(4), deterministic cache
137 * parameters cpuid leaf to find the cache details
138 */
139 for (i = 0; i < num_cache_leaves; i++) {
140 struct cpuid4_info this_leaf;
141
142 int retval;
143
144 retval = cpuid4_cache_lookup(i, &this_leaf);
145 if (retval >= 0) {
146 switch(this_leaf.eax.split.level) {
147 case 1:
148 if (this_leaf.eax.split.type ==
149 CACHE_TYPE_DATA)
150 new_l1d = this_leaf.size/1024;
151 else if (this_leaf.eax.split.type ==
152 CACHE_TYPE_INST)
153 new_l1i = this_leaf.size/1024;
154 break;
155 case 2:
156 new_l2 = this_leaf.size/1024;
157 break;
158 case 3:
159 new_l3 = this_leaf.size/1024;
160 break;
161 default:
162 break;
163 }
164 }
165 }
166 }
167 /*
168 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
169 * trace cache
170 */
171 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1 &&
172 c->x86_vendor != X86_VENDOR_SHANGHAI)
173 {
174 /* supports eax=2 call */
175 int i, j, n;
176 int regs[4];
177 unsigned char *dp = (unsigned char *)regs;
178 int only_trace = 0;
179
180 if (num_cache_leaves != 0 && c->x86 == 15)
181 only_trace = 1;
182
183 /* Number of times to iterate */
184 n = cpuid_eax(2) & 0xFF;
185
186 for ( i = 0 ; i < n ; i++ ) {
187 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
188
189 /* If bit 31 is set, this is an unknown format */
190 for ( j = 0 ; j < 3 ; j++ ) {
191 if ( regs[j] < 0 ) regs[j] = 0;
192 }
193
194 /* Byte 0 is level count, not a descriptor */
195 for ( j = 1 ; j < 16 ; j++ ) {
196 unsigned char des = dp[j];
197 unsigned char k = 0;
198
199 /* look up this descriptor in the table */
200 while (cache_table[k].descriptor != 0)
201 {
202 if (cache_table[k].descriptor == des) {
203 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
204 break;
205 switch (cache_table[k].cache_type) {
206 case LVL_1_INST:
207 l1i += cache_table[k].size;
208 break;
209 case LVL_1_DATA:
210 l1d += cache_table[k].size;
211 break;
212 case LVL_2:
213 l2 += cache_table[k].size;
214 break;
215 case LVL_3:
216 l3 += cache_table[k].size;
217 break;
218 case LVL_TRACE:
219 trace += cache_table[k].size;
220 break;
221 }
222
223 break;
224 }
225
226 k++;
227 }
228 }
229 }
230 }
231
232 if (new_l1d)
233 l1d = new_l1d;
234
235 if (new_l1i)
236 l1i = new_l1i;
237
238 if (new_l2) {
239 l2 = new_l2;
240 }
241
242 if (new_l3) {
243 l3 = new_l3;
244 }
245
246 if (opt_cpu_info) {
247 if (trace)
248 printk("CPU: Trace cache: %dK uops", trace);
249 else if ( l1i )
250 printk("CPU: L1 I cache: %dK", l1i);
251
252 if (l1d)
253 printk(", L1 D cache: %dK\n", l1d);
254 else
255 printk("\n");
256
257 if (l2)
258 printk("CPU: L2 cache: %dK\n", l2);
259
260 if (l3)
261 printk("CPU: L3 cache: %dK\n", l3);
262 }
263
264 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
265 }
266