1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/firmware.h>
26
27 #include "i915_drv.h"
28 #include "i915_reg.h"
29 #include "intel_de.h"
30 #include "intel_dmc.h"
31
32 /**
33 * DOC: DMC Firmware Support
34 *
35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
36 * engine to save and restore the state of display engine when it enter into
37 * low-power state and comes back to normal.
38 */
39
40 #define DMC_PATH(platform, major, minor) \
41 "i915/" \
42 __stringify(platform) "_dmc_ver" \
43 __stringify(major) "_" \
44 __stringify(minor) ".bin"
45
46 #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
47
48 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 12)
49 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 12)
50 MODULE_FIRMWARE(ADLP_DMC_PATH);
51
52 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
53 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
54 MODULE_FIRMWARE(ADLS_DMC_PATH);
55
56 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02)
57 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
58 MODULE_FIRMWARE(DG1_DMC_PATH);
59
60 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03)
61 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3)
62 MODULE_FIRMWARE(RKL_DMC_PATH);
63
64 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12)
65 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12)
66 MODULE_FIRMWARE(TGL_DMC_PATH);
67
68 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
69 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9)
70 #define ICL_DMC_MAX_FW_SIZE 0x6000
71 MODULE_FIRMWARE(ICL_DMC_PATH);
72
73 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
74 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
75 #define GLK_DMC_MAX_FW_SIZE 0x4000
76 MODULE_FIRMWARE(GLK_DMC_PATH);
77
78 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04)
79 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
80 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
81 MODULE_FIRMWARE(KBL_DMC_PATH);
82
83 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
84 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27)
85 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
86 MODULE_FIRMWARE(SKL_DMC_PATH);
87
88 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07)
89 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
90 #define BXT_DMC_MAX_FW_SIZE 0x3000
91 MODULE_FIRMWARE(BXT_DMC_PATH);
92
93 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
94 #define PACKAGE_MAX_FW_INFO_ENTRIES 20
95 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
96 #define DMC_V1_MAX_MMIO_COUNT 8
97 #define DMC_V3_MAX_MMIO_COUNT 20
98 #define DMC_V1_MMIO_START_RANGE 0x80000
99
100 struct intel_css_header {
101 /* 0x09 for DMC */
102 u32 module_type;
103
104 /* Includes the DMC specific header in dwords */
105 u32 header_len;
106
107 /* always value would be 0x10000 */
108 u32 header_ver;
109
110 /* Not used */
111 u32 module_id;
112
113 /* Not used */
114 u32 module_vendor;
115
116 /* in YYYYMMDD format */
117 u32 date;
118
119 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
120 u32 size;
121
122 /* Not used */
123 u32 key_size;
124
125 /* Not used */
126 u32 modulus_size;
127
128 /* Not used */
129 u32 exponent_size;
130
131 /* Not used */
132 u32 reserved1[12];
133
134 /* Major Minor */
135 u32 version;
136
137 /* Not used */
138 u32 reserved2[8];
139
140 /* Not used */
141 u32 kernel_header_info;
142 } __packed;
143
144 struct intel_fw_info {
145 u8 reserved1;
146
147 /* reserved on package_header version 1, must be 0 on version 2 */
148 u8 dmc_id;
149
150 /* Stepping (A, B, C, ..., *). * is a wildcard */
151 char stepping;
152
153 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
154 char substepping;
155
156 u32 offset;
157 u32 reserved2;
158 } __packed;
159
160 struct intel_package_header {
161 /* DMC container header length in dwords */
162 u8 header_len;
163
164 /* 0x01, 0x02 */
165 u8 header_ver;
166
167 u8 reserved[10];
168
169 /* Number of valid entries in the FWInfo array below */
170 u32 num_entries;
171 } __packed;
172
173 struct intel_dmc_header_base {
174 /* always value would be 0x40403E3E */
175 u32 signature;
176
177 /* DMC binary header length */
178 u8 header_len;
179
180 /* 0x01 */
181 u8 header_ver;
182
183 /* Reserved */
184 u16 dmcc_ver;
185
186 /* Major, Minor */
187 u32 project;
188
189 /* Firmware program size (excluding header) in dwords */
190 u32 fw_size;
191
192 /* Major Minor version */
193 u32 fw_version;
194 } __packed;
195
196 struct intel_dmc_header_v1 {
197 struct intel_dmc_header_base base;
198
199 /* Number of valid MMIO cycles present. */
200 u32 mmio_count;
201
202 /* MMIO address */
203 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
204
205 /* MMIO data */
206 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
207
208 /* FW filename */
209 char dfile[32];
210
211 u32 reserved1[2];
212 } __packed;
213
214 struct intel_dmc_header_v3 {
215 struct intel_dmc_header_base base;
216
217 /* DMC RAM start MMIO address */
218 u32 start_mmioaddr;
219
220 u32 reserved[9];
221
222 /* FW filename */
223 char dfile[32];
224
225 /* Number of valid MMIO cycles present. */
226 u32 mmio_count;
227
228 /* MMIO address */
229 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
230
231 /* MMIO data */
232 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
233 } __packed;
234
235 struct stepping_info {
236 char stepping;
237 char substepping;
238 };
239
intel_dmc_has_payload(struct drm_i915_private * i915)240 bool intel_dmc_has_payload(struct drm_i915_private *i915)
241 {
242 return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
243 }
244
245 static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private * i915,struct stepping_info * si)246 intel_get_stepping_info(struct drm_i915_private *i915,
247 struct stepping_info *si)
248 {
249 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step);
250
251 si->stepping = step_name[0];
252 si->substepping = step_name[1];
253 return si;
254 }
255
gen9_set_dc_state_debugmask(struct drm_i915_private * dev_priv)256 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
257 {
258 /* The below bit doesn't need to be cleared ever afterwards */
259 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
260 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
261 intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
262 }
263
264 /**
265 * intel_dmc_load_program() - write the firmware from memory to register.
266 * @dev_priv: i915 drm device.
267 *
268 * DMC firmware is read from a .bin file and kept in internal memory one time.
269 * Everytime display comes back from low power state this function is called to
270 * copy the firmware from internal memory to registers.
271 */
intel_dmc_load_program(struct drm_i915_private * dev_priv)272 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
273 {
274 struct intel_dmc *dmc = &dev_priv->dmc;
275 u32 id, i;
276
277 if (!HAS_DMC(dev_priv)) {
278 drm_err(&dev_priv->drm,
279 "No DMC support available for this platform\n");
280 return;
281 }
282
283 if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
284 drm_err(&dev_priv->drm,
285 "Tried to program CSR with empty payload\n");
286 return;
287 }
288
289 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
290
291 preempt_disable();
292
293 for (id = 0; id < DMC_FW_MAX; id++) {
294 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
295 intel_uncore_write_fw(&dev_priv->uncore,
296 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
297 dmc->dmc_info[id].payload[i]);
298 }
299 }
300
301 preempt_enable();
302
303 for (id = 0; id < DMC_FW_MAX; id++) {
304 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
305 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
306 dmc->dmc_info[id].mmiodata[i]);
307 }
308 }
309
310 dev_priv->dmc.dc_state = 0;
311
312 gen9_set_dc_state_debugmask(dev_priv);
313 }
314
fw_info_matches_stepping(const struct intel_fw_info * fw_info,const struct stepping_info * si)315 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
316 const struct stepping_info *si)
317 {
318 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
319 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
320 /*
321 * If we don't find a more specific one from above two checks, we
322 * then check for the generic one to be sure to work even with
323 * "broken firmware"
324 */
325 (si->stepping == '*' && si->substepping == fw_info->substepping) ||
326 (fw_info->stepping == '*' && fw_info->substepping == '*'))
327 return true;
328
329 return false;
330 }
331
332 /*
333 * Search fw_info table for dmc_offset to find firmware binary: num_entries is
334 * already sanitized.
335 */
dmc_set_fw_offset(struct intel_dmc * dmc,const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver)336 static void dmc_set_fw_offset(struct intel_dmc *dmc,
337 const struct intel_fw_info *fw_info,
338 unsigned int num_entries,
339 const struct stepping_info *si,
340 u8 package_ver)
341 {
342 unsigned int i, id;
343
344 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
345
346 for (i = 0; i < num_entries; i++) {
347 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
348
349 if (id >= DMC_FW_MAX) {
350 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
351 continue;
352 }
353
354 /* More specific versions come first, so we don't even have to
355 * check for the stepping since we already found a previous FW
356 * for this id.
357 */
358 if (dmc->dmc_info[id].present)
359 continue;
360
361 if (fw_info_matches_stepping(&fw_info[i], si)) {
362 dmc->dmc_info[id].present = true;
363 dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
364 }
365 }
366 }
367
parse_dmc_fw_header(struct intel_dmc * dmc,const struct intel_dmc_header_base * dmc_header,size_t rem_size,u8 dmc_id)368 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
369 const struct intel_dmc_header_base *dmc_header,
370 size_t rem_size, u8 dmc_id)
371 {
372 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
373 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
374 unsigned int header_len_bytes, dmc_header_size, payload_size, i;
375 const u32 *mmioaddr, *mmiodata;
376 u32 mmio_count, mmio_count_max, start_mmioaddr;
377 u8 *payload;
378
379 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
380 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
381
382 /*
383 * Check if we can access common fields, we will checkc again below
384 * after we have read the version
385 */
386 if (rem_size < sizeof(struct intel_dmc_header_base))
387 goto error_truncated;
388
389 /* Cope with small differences between v1 and v3 */
390 if (dmc_header->header_ver == 3) {
391 const struct intel_dmc_header_v3 *v3 =
392 (const struct intel_dmc_header_v3 *)dmc_header;
393
394 if (rem_size < sizeof(struct intel_dmc_header_v3))
395 goto error_truncated;
396
397 mmioaddr = v3->mmioaddr;
398 mmiodata = v3->mmiodata;
399 mmio_count = v3->mmio_count;
400 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
401 /* header_len is in dwords */
402 header_len_bytes = dmc_header->header_len * 4;
403 start_mmioaddr = v3->start_mmioaddr;
404 dmc_header_size = sizeof(*v3);
405 } else if (dmc_header->header_ver == 1) {
406 const struct intel_dmc_header_v1 *v1 =
407 (const struct intel_dmc_header_v1 *)dmc_header;
408
409 if (rem_size < sizeof(struct intel_dmc_header_v1))
410 goto error_truncated;
411
412 mmioaddr = v1->mmioaddr;
413 mmiodata = v1->mmiodata;
414 mmio_count = v1->mmio_count;
415 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
416 header_len_bytes = dmc_header->header_len;
417 start_mmioaddr = DMC_V1_MMIO_START_RANGE;
418 dmc_header_size = sizeof(*v1);
419 } else {
420 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
421 dmc_header->header_ver);
422 return 0;
423 }
424
425 if (header_len_bytes != dmc_header_size) {
426 drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
427 "(%u bytes)\n", header_len_bytes);
428 return 0;
429 }
430
431 /* Cache the dmc header info. */
432 if (mmio_count > mmio_count_max) {
433 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
434 return 0;
435 }
436
437 for (i = 0; i < mmio_count; i++) {
438 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
439 dmc_info->mmiodata[i] = mmiodata[i];
440 }
441 dmc_info->mmio_count = mmio_count;
442 dmc_info->start_mmioaddr = start_mmioaddr;
443
444 rem_size -= header_len_bytes;
445
446 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
447 payload_size = dmc_header->fw_size * 4;
448 if (rem_size < payload_size)
449 goto error_truncated;
450
451 if (payload_size > dmc->max_fw_size) {
452 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
453 return 0;
454 }
455 dmc_info->dmc_fw_size = dmc_header->fw_size;
456
457 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
458 if (!dmc_info->payload)
459 return 0;
460
461 payload = (u8 *)(dmc_header) + header_len_bytes;
462 memcpy(dmc_info->payload, payload, payload_size);
463
464 return header_len_bytes + payload_size;
465
466 error_truncated:
467 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
468 return 0;
469 }
470
471 static u32
parse_dmc_fw_package(struct intel_dmc * dmc,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size)472 parse_dmc_fw_package(struct intel_dmc *dmc,
473 const struct intel_package_header *package_header,
474 const struct stepping_info *si,
475 size_t rem_size)
476 {
477 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
478 u32 package_size = sizeof(struct intel_package_header);
479 u32 num_entries, max_entries;
480 const struct intel_fw_info *fw_info;
481
482 if (rem_size < package_size)
483 goto error_truncated;
484
485 if (package_header->header_ver == 1) {
486 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
487 } else if (package_header->header_ver == 2) {
488 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
489 } else {
490 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
491 package_header->header_ver);
492 return 0;
493 }
494
495 /*
496 * We should always have space for max_entries,
497 * even if not all are used
498 */
499 package_size += max_entries * sizeof(struct intel_fw_info);
500 if (rem_size < package_size)
501 goto error_truncated;
502
503 if (package_header->header_len * 4 != package_size) {
504 drm_err(&i915->drm, "DMC firmware has wrong package header length "
505 "(%u bytes)\n", package_size);
506 return 0;
507 }
508
509 num_entries = package_header->num_entries;
510 if (WARN_ON(package_header->num_entries > max_entries))
511 num_entries = max_entries;
512
513 fw_info = (const struct intel_fw_info *)
514 ((u8 *)package_header + sizeof(*package_header));
515 dmc_set_fw_offset(dmc, fw_info, num_entries, si,
516 package_header->header_ver);
517
518 /* dmc_offset is in dwords */
519 return package_size;
520
521 error_truncated:
522 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
523 return 0;
524 }
525
526 /* Return number of bytes parsed or 0 on error */
parse_dmc_fw_css(struct intel_dmc * dmc,struct intel_css_header * css_header,size_t rem_size)527 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
528 struct intel_css_header *css_header,
529 size_t rem_size)
530 {
531 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
532
533 if (rem_size < sizeof(struct intel_css_header)) {
534 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
535 return 0;
536 }
537
538 if (sizeof(struct intel_css_header) !=
539 (css_header->header_len * 4)) {
540 drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
541 "(%u bytes)\n",
542 (css_header->header_len * 4));
543 return 0;
544 }
545
546 if (dmc->required_version &&
547 css_header->version != dmc->required_version) {
548 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u,"
549 " please use v%u.%u\n",
550 DMC_VERSION_MAJOR(css_header->version),
551 DMC_VERSION_MINOR(css_header->version),
552 DMC_VERSION_MAJOR(dmc->required_version),
553 DMC_VERSION_MINOR(dmc->required_version));
554 return 0;
555 }
556
557 dmc->version = css_header->version;
558
559 return sizeof(struct intel_css_header);
560 }
561
parse_dmc_fw(struct drm_i915_private * dev_priv,const struct firmware * fw)562 static void parse_dmc_fw(struct drm_i915_private *dev_priv,
563 const struct firmware *fw)
564 {
565 struct intel_css_header *css_header;
566 struct intel_package_header *package_header;
567 struct intel_dmc_header_base *dmc_header;
568 struct intel_dmc *dmc = &dev_priv->dmc;
569 struct stepping_info display_info = { '*', '*'};
570 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
571 u32 readcount = 0;
572 u32 r, offset;
573 int id;
574
575 if (!fw)
576 return;
577
578 /* Extract CSS Header information */
579 css_header = (struct intel_css_header *)fw->data;
580 r = parse_dmc_fw_css(dmc, css_header, fw->size);
581 if (!r)
582 return;
583
584 readcount += r;
585
586 /* Extract Package Header information */
587 package_header = (struct intel_package_header *)&fw->data[readcount];
588 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
589 if (!r)
590 return;
591
592 readcount += r;
593
594 for (id = 0; id < DMC_FW_MAX; id++) {
595 if (!dev_priv->dmc.dmc_info[id].present)
596 continue;
597
598 offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
599 if (offset > fw->size) {
600 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
601 continue;
602 }
603
604 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
605 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
606 }
607 }
608
intel_dmc_runtime_pm_get(struct drm_i915_private * dev_priv)609 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
610 {
611 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
612 dev_priv->dmc.wakeref =
613 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
614 }
615
intel_dmc_runtime_pm_put(struct drm_i915_private * dev_priv)616 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
617 {
618 intel_wakeref_t wakeref __maybe_unused =
619 fetch_and_zero(&dev_priv->dmc.wakeref);
620
621 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
622 }
623
dmc_load_work_fn(struct work_struct * work)624 static void dmc_load_work_fn(struct work_struct *work)
625 {
626 struct drm_i915_private *dev_priv;
627 struct intel_dmc *dmc;
628 const struct firmware *fw = NULL;
629
630 dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
631 dmc = &dev_priv->dmc;
632
633 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
634 parse_dmc_fw(dev_priv, fw);
635
636 if (intel_dmc_has_payload(dev_priv)) {
637 intel_dmc_load_program(dev_priv);
638 intel_dmc_runtime_pm_put(dev_priv);
639
640 drm_info(&dev_priv->drm,
641 "Finished loading DMC firmware %s (v%u.%u)\n",
642 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
643 DMC_VERSION_MINOR(dmc->version));
644 } else {
645 drm_notice(&dev_priv->drm,
646 "Failed to load DMC firmware %s."
647 " Disabling runtime power management.\n",
648 dmc->fw_path);
649 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
650 INTEL_UC_FIRMWARE_URL);
651 }
652
653 release_firmware(fw);
654 }
655
656 /**
657 * intel_dmc_ucode_init() - initialize the firmware loading.
658 * @dev_priv: i915 drm device.
659 *
660 * This function is called at the time of loading the display driver to read
661 * firmware from a .bin file and copied into a internal memory.
662 */
intel_dmc_ucode_init(struct drm_i915_private * dev_priv)663 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
664 {
665 struct intel_dmc *dmc = &dev_priv->dmc;
666
667 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
668
669 if (!HAS_DMC(dev_priv))
670 return;
671
672 /*
673 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
674 * runtime-suspend.
675 *
676 * On error, we return with the rpm wakeref held to prevent runtime
677 * suspend as runtime suspend *requires* a working DMC for whatever
678 * reason.
679 */
680 intel_dmc_runtime_pm_get(dev_priv);
681
682 if (IS_ALDERLAKE_P(dev_priv)) {
683 dmc->fw_path = ADLP_DMC_PATH;
684 dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
685 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
686 } else if (IS_ALDERLAKE_S(dev_priv)) {
687 dmc->fw_path = ADLS_DMC_PATH;
688 dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
689 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
690 } else if (IS_DG1(dev_priv)) {
691 dmc->fw_path = DG1_DMC_PATH;
692 dmc->required_version = DG1_DMC_VERSION_REQUIRED;
693 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
694 } else if (IS_ROCKETLAKE(dev_priv)) {
695 dmc->fw_path = RKL_DMC_PATH;
696 dmc->required_version = RKL_DMC_VERSION_REQUIRED;
697 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
698 } else if (DISPLAY_VER(dev_priv) >= 12) {
699 dmc->fw_path = TGL_DMC_PATH;
700 dmc->required_version = TGL_DMC_VERSION_REQUIRED;
701 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
702 } else if (DISPLAY_VER(dev_priv) == 11) {
703 dmc->fw_path = ICL_DMC_PATH;
704 dmc->required_version = ICL_DMC_VERSION_REQUIRED;
705 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
706 } else if (IS_GEMINILAKE(dev_priv)) {
707 dmc->fw_path = GLK_DMC_PATH;
708 dmc->required_version = GLK_DMC_VERSION_REQUIRED;
709 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
710 } else if (IS_KABYLAKE(dev_priv) ||
711 IS_COFFEELAKE(dev_priv) ||
712 IS_COMETLAKE(dev_priv)) {
713 dmc->fw_path = KBL_DMC_PATH;
714 dmc->required_version = KBL_DMC_VERSION_REQUIRED;
715 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
716 } else if (IS_SKYLAKE(dev_priv)) {
717 dmc->fw_path = SKL_DMC_PATH;
718 dmc->required_version = SKL_DMC_VERSION_REQUIRED;
719 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
720 } else if (IS_BROXTON(dev_priv)) {
721 dmc->fw_path = BXT_DMC_PATH;
722 dmc->required_version = BXT_DMC_VERSION_REQUIRED;
723 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
724 }
725
726 if (dev_priv->params.dmc_firmware_path) {
727 if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
728 dmc->fw_path = NULL;
729 drm_info(&dev_priv->drm,
730 "Disabling DMC firmware and runtime PM\n");
731 return;
732 }
733
734 dmc->fw_path = dev_priv->params.dmc_firmware_path;
735 /* Bypass version check for firmware override. */
736 dmc->required_version = 0;
737 }
738
739 if (!dmc->fw_path) {
740 drm_dbg_kms(&dev_priv->drm,
741 "No known DMC firmware for platform, disabling runtime PM\n");
742 return;
743 }
744
745 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
746 schedule_work(&dev_priv->dmc.work);
747 }
748
749 /**
750 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
751 * @dev_priv: i915 drm device
752 *
753 * Prepare the DMC firmware before entering system suspend. This includes
754 * flushing pending work items and releasing any resources acquired during
755 * init.
756 */
intel_dmc_ucode_suspend(struct drm_i915_private * dev_priv)757 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
758 {
759 if (!HAS_DMC(dev_priv))
760 return;
761
762 flush_work(&dev_priv->dmc.work);
763
764 /* Drop the reference held in case DMC isn't loaded. */
765 if (!intel_dmc_has_payload(dev_priv))
766 intel_dmc_runtime_pm_put(dev_priv);
767 }
768
769 /**
770 * intel_dmc_ucode_resume() - init DMC firmware during system resume
771 * @dev_priv: i915 drm device
772 *
773 * Reinitialize the DMC firmware during system resume, reacquiring any
774 * resources released in intel_dmc_ucode_suspend().
775 */
intel_dmc_ucode_resume(struct drm_i915_private * dev_priv)776 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
777 {
778 if (!HAS_DMC(dev_priv))
779 return;
780
781 /*
782 * Reacquire the reference to keep RPM disabled in case DMC isn't
783 * loaded.
784 */
785 if (!intel_dmc_has_payload(dev_priv))
786 intel_dmc_runtime_pm_get(dev_priv);
787 }
788
789 /**
790 * intel_dmc_ucode_fini() - unload the DMC firmware.
791 * @dev_priv: i915 drm device.
792 *
793 * Firmmware unloading includes freeing the internal memory and reset the
794 * firmware loading status.
795 */
intel_dmc_ucode_fini(struct drm_i915_private * dev_priv)796 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
797 {
798 int id;
799
800 if (!HAS_DMC(dev_priv))
801 return;
802
803 intel_dmc_ucode_suspend(dev_priv);
804 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
805
806 for (id = 0; id < DMC_FW_MAX; id++)
807 kfree(dev_priv->dmc.dmc_info[id].payload);
808 }
809