1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2013-2021 Intel Corporation
4  *
5  * LPT/WPT IOSF sideband.
6  */
7 
8 #include "i915_drv.h"
9 #include "intel_sbi.h"
10 
11 /* SBI access */
intel_sbi_rw(struct drm_i915_private * i915,u16 reg,enum intel_sbi_destination destination,u32 * val,bool is_read)12 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
13 			enum intel_sbi_destination destination,
14 			u32 *val, bool is_read)
15 {
16 	struct intel_uncore *uncore = &i915->uncore;
17 	u32 cmd;
18 
19 	lockdep_assert_held(&i915->sb_lock);
20 
21 	if (intel_wait_for_register_fw(uncore,
22 				       SBI_CTL_STAT, SBI_BUSY, 0,
23 				       100)) {
24 		drm_err(&i915->drm,
25 			"timeout waiting for SBI to become ready\n");
26 		return -EBUSY;
27 	}
28 
29 	intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
30 	intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
31 
32 	if (destination == SBI_ICLK)
33 		cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
34 	else
35 		cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
36 	if (!is_read)
37 		cmd |= BIT(8);
38 	intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
39 
40 	if (__intel_wait_for_register_fw(uncore,
41 					 SBI_CTL_STAT, SBI_BUSY, 0,
42 					 100, 100, &cmd)) {
43 		drm_err(&i915->drm,
44 			"timeout waiting for SBI to complete read\n");
45 		return -ETIMEDOUT;
46 	}
47 
48 	if (cmd & SBI_RESPONSE_FAIL) {
49 		drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
50 		return -ENXIO;
51 	}
52 
53 	if (is_read)
54 		*val = intel_uncore_read_fw(uncore, SBI_DATA);
55 
56 	return 0;
57 }
58 
intel_sbi_read(struct drm_i915_private * i915,u16 reg,enum intel_sbi_destination destination)59 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
60 		   enum intel_sbi_destination destination)
61 {
62 	u32 result = 0;
63 
64 	intel_sbi_rw(i915, reg, destination, &result, true);
65 
66 	return result;
67 }
68 
intel_sbi_write(struct drm_i915_private * i915,u16 reg,u32 value,enum intel_sbi_destination destination)69 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
70 		     enum intel_sbi_destination destination)
71 {
72 	intel_sbi_rw(i915, reg, destination, &value, false);
73 }
74