1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions. 4 * 5 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 6 * 7 * Based on drivers/usb/musb/davinci.h 8 * 9 * Copyright (C) 2009 Texas Instruments Incorporated 10 */ 11 #ifndef __DA8XX_MUSB_H__ 12 #define __DA8XX_MUSB_H__ 13 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/gpio.h> 16 17 /* Base address of da8xx usb0 wrapper */ 18 #define DA8XX_USB_OTG_BASE 0x01E00000 19 20 /* Base address of da8xx musb core */ 21 #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) 22 23 /* Timeout for DA8xx usb module */ 24 #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF 25 26 /* 27 * DA8xx platform USB wrapper register overlay. 28 */ 29 struct da8xx_usb_regs { 30 dv_reg revision; 31 dv_reg control; 32 dv_reg status; 33 dv_reg emulation; 34 dv_reg mode; 35 dv_reg autoreq; 36 dv_reg srpfixtime; 37 dv_reg teardown; 38 dv_reg intsrc; 39 dv_reg intsrc_set; 40 dv_reg intsrc_clr; 41 dv_reg intmsk; 42 dv_reg intmsk_set; 43 dv_reg intmsk_clr; 44 dv_reg intsrcmsk; 45 dv_reg eoi; 46 dv_reg intvector; 47 dv_reg grndis_size[4]; 48 }; 49 50 #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) 51 52 /* DA8XX interrupt bits definitions */ 53 #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ 54 #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ 55 #define DA8XX_USB_TXINT_SHIFT 0 56 #define DA8XX_USB_RXINT_SHIFT 8 57 58 #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ 59 #define DA8XX_USB_TXINT_MASK \ 60 (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) 61 #define DA8XX_USB_RXINT_MASK \ 62 (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) 63 64 /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ 65 #define CFGCHIP2_PHYCLKGD (1 << 17) 66 #define CFGCHIP2_VBUSSENSE (1 << 16) 67 #define CFGCHIP2_RESET (1 << 15) 68 #define CFGCHIP2_OTGMODE (3 << 13) 69 #define CFGCHIP2_NO_OVERRIDE (0 << 13) 70 #define CFGCHIP2_FORCE_HOST (1 << 13) 71 #define CFGCHIP2_FORCE_DEVICE (2 << 13) 72 #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) 73 #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) 74 #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) 75 #define CFGCHIP2_PHYPWRDN (1 << 10) 76 #define CFGCHIP2_OTGPWRDN (1 << 9) 77 #define CFGCHIP2_DATPOL (1 << 8) 78 #define CFGCHIP2_USB1SUSPENDM (1 << 7) 79 #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ 80 #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ 81 #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ 82 #define CFGCHIP2_REFFREQ (0xf << 0) 83 #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) 84 #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) 85 #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) 86 87 #define DA8XX_USB_VBUS_GPIO (1 << 15) 88 89 #endif /* __DA8XX_MUSB_H__ */ 90