1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/hab.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/syscounter.h>
20 #include <asm/ptrace.h>
21 #include <asm/armv8/mmu.h>
22 #include <dm/uclass.h>
23 #include <efi_loader.h>
24 #include <env.h>
25 #include <env_internal.h>
26 #include <errno.h>
27 #include <fdt_support.h>
28 #include <fsl_wdog.h>
29 #include <imx_sip.h>
30 #include <linux/arm-smccc.h>
31 #include <linux/bitops.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #if defined(CONFIG_IMX_HAB)
36 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
37 .bank = 1,
38 .word = 3,
39 };
40 #endif
41
timer_init(void)42 int timer_init(void)
43 {
44 #ifdef CONFIG_SPL_BUILD
45 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
46 unsigned long freq = readl(&sctr->cntfid0);
47
48 /* Update with accurate clock frequency */
49 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
50
51 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
52 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
53 #endif
54
55 gd->arch.tbl = 0;
56 gd->arch.tbu = 0;
57
58 return 0;
59 }
60
enable_tzc380(void)61 void enable_tzc380(void)
62 {
63 struct iomuxc_gpr_base_regs *gpr =
64 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
65
66 /* Enable TZASC and lock setting */
67 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
68 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
69 if (is_imx8mm() || is_imx8mn() || is_imx8mp())
70 setbits_le32(&gpr->gpr[10], BIT(1));
71 /*
72 * set Region 0 attribute to allow secure and non-secure
73 * read/write permission. Found some masters like usb dwc3
74 * controllers can't work with secure memory.
75 */
76 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
77 }
78
set_wdog_reset(struct wdog_regs * wdog)79 void set_wdog_reset(struct wdog_regs *wdog)
80 {
81 /*
82 * Output WDOG_B signal to reset external pmic or POR_B decided by
83 * the board design. Without external reset, the peripherals/DDR/
84 * PMIC are not reset, that may cause system working abnormal.
85 * WDZST bit is write-once only bit. Align this bit in kernel,
86 * otherwise kernel code will have no chance to set this bit.
87 */
88 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
89 }
90
91 static struct mm_region imx8m_mem_map[] = {
92 {
93 /* ROM */
94 .virt = 0x0UL,
95 .phys = 0x0UL,
96 .size = 0x100000UL,
97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_OUTER_SHARE
99 }, {
100 /* CAAM */
101 .virt = 0x100000UL,
102 .phys = 0x100000UL,
103 .size = 0x8000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN
107 }, {
108 /* TCM */
109 .virt = 0x7C0000UL,
110 .phys = 0x7C0000UL,
111 .size = 0x80000UL,
112 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
113 PTE_BLOCK_NON_SHARE |
114 PTE_BLOCK_PXN | PTE_BLOCK_UXN
115 }, {
116 /* OCRAM */
117 .virt = 0x900000UL,
118 .phys = 0x900000UL,
119 .size = 0x200000UL,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
121 PTE_BLOCK_OUTER_SHARE
122 }, {
123 /* AIPS */
124 .virt = 0xB00000UL,
125 .phys = 0xB00000UL,
126 .size = 0x3f500000UL,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
128 PTE_BLOCK_NON_SHARE |
129 PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 }, {
131 /* DRAM1 */
132 .virt = 0x40000000UL,
133 .phys = 0x40000000UL,
134 .size = PHYS_SDRAM_SIZE,
135 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
136 PTE_BLOCK_OUTER_SHARE
137 #ifdef PHYS_SDRAM_2_SIZE
138 }, {
139 /* DRAM2 */
140 .virt = 0x100000000UL,
141 .phys = 0x100000000UL,
142 .size = PHYS_SDRAM_2_SIZE,
143 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
144 PTE_BLOCK_OUTER_SHARE
145 #endif
146 }, {
147 /* empty entrie to split table entry 5 if needed when TEEs are used */
148 0,
149 }, {
150 /* List terminator */
151 0,
152 }
153 };
154
155 struct mm_region *mem_map = imx8m_mem_map;
156
imx8m_find_dram_entry_in_mem_map(void)157 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
158 {
159 int i;
160
161 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
162 if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
163 return i;
164
165 hang(); /* Entry not found, this must never happen. */
166 }
167
enable_caches(void)168 void enable_caches(void)
169 {
170 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
171 if (rom_pointer[1]) {
172 /*
173 * TEE are loaded, So the ddr bank structures
174 * have been modified update mmu table accordingly
175 */
176 int i = 0;
177 /*
178 * please make sure that entry initial value matches
179 * imx8m_mem_map for DRAM1
180 */
181 int entry = imx8m_find_dram_entry_in_mem_map();
182 u64 attrs = imx8m_mem_map[entry].attrs;
183
184 while (i < CONFIG_NR_DRAM_BANKS &&
185 entry < ARRAY_SIZE(imx8m_mem_map)) {
186 if (gd->bd->bi_dram[i].start == 0)
187 break;
188 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
189 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
190 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
191 imx8m_mem_map[entry].attrs = attrs;
192 debug("Added memory mapping (%d): %llx %llx\n", entry,
193 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
194 i++; entry++;
195 }
196 }
197
198 icache_enable();
199 dcache_enable();
200 }
201
board_phys_sdram_size(phys_size_t * size)202 __weak int board_phys_sdram_size(phys_size_t *size)
203 {
204 if (!size)
205 return -EINVAL;
206
207 *size = PHYS_SDRAM_SIZE;
208 return 0;
209 }
210
dram_init(void)211 int dram_init(void)
212 {
213 unsigned int entry = imx8m_find_dram_entry_in_mem_map();
214 phys_size_t sdram_size;
215 int ret;
216
217 ret = board_phys_sdram_size(&sdram_size);
218 if (ret)
219 return ret;
220
221 /* rom_pointer[1] contains the size of TEE occupies */
222 if (rom_pointer[1])
223 gd->ram_size = sdram_size - rom_pointer[1];
224 else
225 gd->ram_size = sdram_size;
226
227 /* also update the SDRAM size in the mem_map used externally */
228 imx8m_mem_map[entry].size = sdram_size;
229
230 #ifdef PHYS_SDRAM_2_SIZE
231 gd->ram_size += PHYS_SDRAM_2_SIZE;
232 #endif
233
234 return 0;
235 }
236
dram_init_banksize(void)237 int dram_init_banksize(void)
238 {
239 int bank = 0;
240 int ret;
241 phys_size_t sdram_size;
242
243 ret = board_phys_sdram_size(&sdram_size);
244 if (ret)
245 return ret;
246
247 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
248 if (rom_pointer[1]) {
249 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
250 phys_size_t optee_size = (size_t)rom_pointer[1];
251
252 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
253 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
254 if (++bank >= CONFIG_NR_DRAM_BANKS) {
255 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
256 return -1;
257 }
258
259 gd->bd->bi_dram[bank].start = optee_start + optee_size;
260 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
261 sdram_size - gd->bd->bi_dram[bank].start;
262 }
263 } else {
264 gd->bd->bi_dram[bank].size = sdram_size;
265 }
266
267 #ifdef PHYS_SDRAM_2_SIZE
268 if (++bank >= CONFIG_NR_DRAM_BANKS) {
269 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
270 return -1;
271 }
272 gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
273 gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
274 #endif
275
276 return 0;
277 }
278
get_effective_memsize(void)279 phys_size_t get_effective_memsize(void)
280 {
281 /* return the first bank as effective memory */
282 if (rom_pointer[1])
283 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
284
285 #ifdef PHYS_SDRAM_2_SIZE
286 return gd->ram_size - PHYS_SDRAM_2_SIZE;
287 #else
288 return gd->ram_size;
289 #endif
290 }
291
get_cpu_variant_type(u32 type)292 static u32 get_cpu_variant_type(u32 type)
293 {
294 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
295 struct fuse_bank *bank = &ocotp->bank[1];
296 struct fuse_bank1_regs *fuse =
297 (struct fuse_bank1_regs *)bank->fuse_regs;
298
299 u32 value = readl(&fuse->tester4);
300
301 if (type == MXC_CPU_IMX8MQ) {
302 if ((value & 0x3) == 0x2)
303 return MXC_CPU_IMX8MD;
304 else if (value & 0x200000)
305 return MXC_CPU_IMX8MQL;
306
307 } else if (type == MXC_CPU_IMX8MM) {
308 switch (value & 0x3) {
309 case 2:
310 if (value & 0x1c0000)
311 return MXC_CPU_IMX8MMDL;
312 else
313 return MXC_CPU_IMX8MMD;
314 case 3:
315 if (value & 0x1c0000)
316 return MXC_CPU_IMX8MMSL;
317 else
318 return MXC_CPU_IMX8MMS;
319 default:
320 if (value & 0x1c0000)
321 return MXC_CPU_IMX8MML;
322 break;
323 }
324 } else if (type == MXC_CPU_IMX8MN) {
325 switch (value & 0x3) {
326 case 2:
327 if (value & 0x1000000)
328 return MXC_CPU_IMX8MNDL;
329 else
330 return MXC_CPU_IMX8MND;
331 case 3:
332 if (value & 0x1000000)
333 return MXC_CPU_IMX8MNSL;
334 else
335 return MXC_CPU_IMX8MNS;
336 default:
337 if (value & 0x1000000)
338 return MXC_CPU_IMX8MNL;
339 break;
340 }
341 } else if (type == MXC_CPU_IMX8MP) {
342 u32 value0 = readl(&fuse->tester3);
343 u32 flag = 0;
344
345 if ((value0 & 0xc0000) == 0x80000)
346 return MXC_CPU_IMX8MPD;
347
348 /* vpu disabled */
349 if ((value0 & 0x43000000) == 0x43000000)
350 flag = 1;
351
352 /* npu disabled*/
353 if ((value & 0x8) == 0x8)
354 flag |= (1 << 1);
355
356 /* isp disabled */
357 if ((value & 0x3) == 0x3)
358 flag |= (1 << 2);
359
360 switch (flag) {
361 case 7:
362 return MXC_CPU_IMX8MPL;
363 case 2:
364 return MXC_CPU_IMX8MP6;
365 default:
366 break;
367 }
368
369 }
370
371 return type;
372 }
373
get_cpu_rev(void)374 u32 get_cpu_rev(void)
375 {
376 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
377 u32 reg = readl(&ana_pll->digprog);
378 u32 type = (reg >> 16) & 0xff;
379 u32 major_low = (reg >> 8) & 0xff;
380 u32 rom_version;
381
382 reg &= 0xff;
383
384 /* iMX8MP */
385 if (major_low == 0x43) {
386 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
387 } else if (major_low == 0x42) {
388 /* iMX8MN */
389 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
390 } else if (major_low == 0x41) {
391 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
392 } else {
393 if (reg == CHIP_REV_1_0) {
394 /*
395 * For B0 chip, the DIGPROG is not updated,
396 * it is still TO1.0. we have to check ROM
397 * version or OCOTP_READ_FUSE_DATA.
398 * 0xff0055aa is magic number for B1.
399 */
400 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
401 reg = CHIP_REV_2_1;
402 } else {
403 rom_version =
404 readl((void __iomem *)ROM_VERSION_A0);
405 if (rom_version != CHIP_REV_1_0) {
406 rom_version = readl((void __iomem *)ROM_VERSION_B0);
407 rom_version &= 0xff;
408 if (rom_version == CHIP_REV_2_0)
409 reg = CHIP_REV_2_0;
410 }
411 }
412 }
413
414 type = get_cpu_variant_type(type);
415 }
416
417 return (type << 12) | reg;
418 }
419
imx_set_wdog_powerdown(bool enable)420 static void imx_set_wdog_powerdown(bool enable)
421 {
422 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
423 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
424 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
425
426 /* Write to the PDE (Power Down Enable) bit */
427 writew(enable, &wdog1->wmcr);
428 writew(enable, &wdog2->wmcr);
429 writew(enable, &wdog3->wmcr);
430 }
431
arch_cpu_init_dm(void)432 int arch_cpu_init_dm(void)
433 {
434 struct udevice *dev;
435 int ret;
436
437 if (CONFIG_IS_ENABLED(CLK)) {
438 ret = uclass_get_device_by_name(UCLASS_CLK,
439 "clock-controller@30380000",
440 &dev);
441 if (ret < 0) {
442 printf("Failed to find clock node. Check device tree\n");
443 return ret;
444 }
445 }
446
447 return 0;
448 }
449
arch_cpu_init(void)450 int arch_cpu_init(void)
451 {
452 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
453 /*
454 * ROM might disable clock for SCTR,
455 * enable the clock before timer_init.
456 */
457 if (IS_ENABLED(CONFIG_SPL_BUILD))
458 clock_enable(CCGR_SCTR, 1);
459 /*
460 * Init timer at very early state, because sscg pll setting
461 * will use it
462 */
463 timer_init();
464
465 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
466 clock_init();
467 imx_set_wdog_powerdown(false);
468
469 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
470 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
471 is_imx8mnsl() || is_imx8mpd()) {
472 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
473 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
474 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
475 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
476 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
477
478 writel(0x1, &pgc_core2->pgcr);
479 writel(0x1, &pgc_core3->pgcr);
480 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
481 writel(0x1, &pgc_core1->pgcr);
482 writel(0xE, &gpc->cpu_pgc_dn_trg);
483 } else {
484 writel(0xC, &gpc->cpu_pgc_dn_trg);
485 }
486 }
487 }
488
489 if (is_imx8mq()) {
490 clock_enable(CCGR_OCOTP, 1);
491 if (readl(&ocotp->ctrl) & 0x200)
492 writel(0x200, &ocotp->ctrl_clr);
493 }
494
495 return 0;
496 }
497
498 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
499 struct rom_api *g_rom_api = (struct rom_api *)0x980;
500
get_boot_device(void)501 enum boot_device get_boot_device(void)
502 {
503 volatile gd_t *pgd = gd;
504 int ret;
505 u32 boot;
506 u16 boot_type;
507 u8 boot_instance;
508 enum boot_device boot_dev = SD1_BOOT;
509
510 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
511 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
512 gd = pgd;
513
514 if (ret != ROM_API_OKAY) {
515 puts("ROMAPI: failure at query_boot_info\n");
516 return -1;
517 }
518
519 boot_type = boot >> 16;
520 boot_instance = (boot >> 8) & 0xff;
521
522 switch (boot_type) {
523 case BT_DEV_TYPE_SD:
524 boot_dev = boot_instance + SD1_BOOT;
525 break;
526 case BT_DEV_TYPE_MMC:
527 boot_dev = boot_instance + MMC1_BOOT;
528 break;
529 case BT_DEV_TYPE_NAND:
530 boot_dev = NAND_BOOT;
531 break;
532 case BT_DEV_TYPE_FLEXSPINOR:
533 boot_dev = QSPI_BOOT;
534 break;
535 case BT_DEV_TYPE_USB:
536 boot_dev = USB_BOOT;
537 break;
538 default:
539 break;
540 }
541
542 return boot_dev;
543 }
544 #endif
545
is_usb_boot(void)546 bool is_usb_boot(void)
547 {
548 return get_boot_device() == USB_BOOT;
549 }
550
551 #ifdef CONFIG_OF_SYSTEM_SETUP
check_fdt_new_path(void * blob)552 bool check_fdt_new_path(void *blob)
553 {
554 const char *soc_path = "/soc@0";
555 int nodeoff;
556
557 nodeoff = fdt_path_offset(blob, soc_path);
558 if (nodeoff < 0)
559 return false;
560
561 return true;
562 }
563
disable_fdt_nodes(void * blob,const char * const nodes_path[],int size_array)564 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
565 {
566 int i = 0;
567 int rc;
568 int nodeoff;
569 const char *status = "disabled";
570
571 for (i = 0; i < size_array; i++) {
572 nodeoff = fdt_path_offset(blob, nodes_path[i]);
573 if (nodeoff < 0)
574 continue; /* Not found, skip it */
575
576 printf("Found %s node\n", nodes_path[i]);
577
578 add_status:
579 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
580 if (rc) {
581 if (rc == -FDT_ERR_NOSPACE) {
582 rc = fdt_increase_size(blob, 512);
583 if (!rc)
584 goto add_status;
585 }
586 printf("Unable to update property %s:%s, err=%s\n",
587 nodes_path[i], "status", fdt_strerror(rc));
588 } else {
589 printf("Modify %s:%s disabled\n",
590 nodes_path[i], "status");
591 }
592 }
593
594 return 0;
595 }
596
597 #ifdef CONFIG_IMX8MQ
check_dcss_fused(void)598 bool check_dcss_fused(void)
599 {
600 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
601 struct fuse_bank *bank = &ocotp->bank[1];
602 struct fuse_bank1_regs *fuse =
603 (struct fuse_bank1_regs *)bank->fuse_regs;
604 u32 value = readl(&fuse->tester4);
605
606 if (value & 0x4000000)
607 return true;
608
609 return false;
610 }
611
disable_mipi_dsi_nodes(void * blob)612 static int disable_mipi_dsi_nodes(void *blob)
613 {
614 static const char * const nodes_path[] = {
615 "/mipi_dsi@30A00000",
616 "/mipi_dsi_bridge@30A00000",
617 "/dsi_phy@30A00300",
618 "/soc@0/bus@30800000/mipi_dsi@30a00000",
619 "/soc@0/bus@30800000/dphy@30a00300"
620 };
621
622 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
623 }
624
disable_dcss_nodes(void * blob)625 static int disable_dcss_nodes(void *blob)
626 {
627 static const char * const nodes_path[] = {
628 "/dcss@0x32e00000",
629 "/dcss@32e00000",
630 "/hdmi@32c00000",
631 "/hdmi_cec@32c33800",
632 "/hdmi_drm@32c00000",
633 "/display-subsystem",
634 "/sound-hdmi",
635 "/sound-hdmi-arc",
636 "/soc@0/bus@32c00000/display-controller@32e00000",
637 "/soc@0/bus@32c00000/hdmi@32c00000",
638 };
639
640 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
641 }
642
check_mipi_dsi_nodes(void * blob)643 static int check_mipi_dsi_nodes(void *blob)
644 {
645 static const char * const lcdif_path[] = {
646 "/lcdif@30320000",
647 "/soc@0/bus@30000000/lcdif@30320000"
648 };
649 static const char * const mipi_dsi_path[] = {
650 "/mipi_dsi@30A00000",
651 "/soc@0/bus@30800000/mipi_dsi@30a00000"
652 };
653 static const char * const lcdif_ep_path[] = {
654 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
655 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint"
656 };
657 static const char * const mipi_dsi_ep_path[] = {
658 "/mipi_dsi@30A00000/port@1/endpoint",
659 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint"
660 };
661
662 int lookup_node;
663 int nodeoff;
664 bool new_path = check_fdt_new_path(blob);
665 int i = new_path ? 1 : 0;
666
667 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
668 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
669 /*
670 * If can't find lcdif node or lcdif node is disabled,
671 * then disable all mipi dsi, since they only can input
672 * from DCSS
673 */
674 return disable_mipi_dsi_nodes(blob);
675 }
676
677 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
678 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
679 return 0;
680
681 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
682 if (nodeoff < 0) {
683 /*
684 * If can't find lcdif endpoint, then disable all mipi dsi,
685 * since they only can input from DCSS
686 */
687 return disable_mipi_dsi_nodes(blob);
688 }
689
690 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
691 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
692
693 if (nodeoff > 0 && nodeoff == lookup_node)
694 return 0;
695
696 return disable_mipi_dsi_nodes(blob);
697 }
698 #endif
699
disable_vpu_nodes(void * blob)700 int disable_vpu_nodes(void *blob)
701 {
702 static const char * const nodes_path_8mq[] = {
703 "/vpu@38300000",
704 "/soc@0/vpu@38300000"
705 };
706
707 static const char * const nodes_path_8mm[] = {
708 "/vpu_g1@38300000",
709 "/vpu_g2@38310000",
710 "/vpu_h1@38320000"
711 };
712
713 static const char * const nodes_path_8mp[] = {
714 "/vpu_g1@38300000",
715 "/vpu_g2@38310000",
716 "/vpu_vc8000e@38320000"
717 };
718
719 if (is_imx8mq())
720 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
721 else if (is_imx8mm())
722 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
723 else if (is_imx8mp())
724 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
725 else
726 return -EPERM;
727 }
728
disable_gpu_nodes(void * blob)729 int disable_gpu_nodes(void *blob)
730 {
731 static const char * const nodes_path_8mn[] = {
732 "/gpu@38000000"
733 };
734
735 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
736 }
737
disable_npu_nodes(void * blob)738 int disable_npu_nodes(void *blob)
739 {
740 static const char * const nodes_path_8mp[] = {
741 "/vipsi@38500000"
742 };
743
744 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
745 }
746
disable_isp_nodes(void * blob)747 int disable_isp_nodes(void *blob)
748 {
749 static const char * const nodes_path_8mp[] = {
750 "/soc@0/bus@32c00000/camera/isp@32e10000",
751 "/soc@0/bus@32c00000/camera/isp@32e20000"
752 };
753
754 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
755 }
756
disable_dsp_nodes(void * blob)757 int disable_dsp_nodes(void *blob)
758 {
759 static const char * const nodes_path_8mp[] = {
760 "/dsp@3b6e8000"
761 };
762
763 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
764 }
765
disable_cpu_nodes(void * blob,u32 disabled_cores)766 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
767 {
768 static const char * const nodes_path[] = {
769 "/cpus/cpu@1",
770 "/cpus/cpu@2",
771 "/cpus/cpu@3",
772 };
773 u32 i = 0;
774 int rc;
775 int nodeoff;
776
777 if (disabled_cores > 3)
778 return -EINVAL;
779
780 i = 3 - disabled_cores;
781
782 for (; i < 3; i++) {
783 nodeoff = fdt_path_offset(blob, nodes_path[i]);
784 if (nodeoff < 0)
785 continue; /* Not found, skip it */
786
787 debug("Found %s node\n", nodes_path[i]);
788
789 rc = fdt_del_node(blob, nodeoff);
790 if (rc < 0) {
791 printf("Unable to delete node %s, err=%s\n",
792 nodes_path[i], fdt_strerror(rc));
793 } else {
794 printf("Delete node %s\n", nodes_path[i]);
795 }
796 }
797
798 return 0;
799 }
800
ft_system_setup(void * blob,struct bd_info * bd)801 int ft_system_setup(void *blob, struct bd_info *bd)
802 {
803 #ifdef CONFIG_IMX8MQ
804 int i = 0;
805 int rc;
806 int nodeoff;
807
808 if (get_boot_device() == USB_BOOT) {
809 disable_dcss_nodes(blob);
810
811 bool new_path = check_fdt_new_path(blob);
812 int v = new_path ? 1 : 0;
813 static const char * const usb_dwc3_path[] = {
814 "/usb@38100000/dwc3",
815 "/soc@0/usb@38100000"
816 };
817
818 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
819 if (nodeoff >= 0) {
820 const char *speed = "high-speed";
821
822 printf("Found %s node\n", usb_dwc3_path[v]);
823
824 usb_modify_speed:
825
826 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
827 if (rc) {
828 if (rc == -FDT_ERR_NOSPACE) {
829 rc = fdt_increase_size(blob, 512);
830 if (!rc)
831 goto usb_modify_speed;
832 }
833 printf("Unable to set property %s:%s, err=%s\n",
834 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
835 } else {
836 printf("Modify %s:%s = %s\n",
837 usb_dwc3_path[v], "maximum-speed", speed);
838 }
839 } else {
840 printf("Can't found %s node\n", usb_dwc3_path[v]);
841 }
842 }
843
844 /* Disable the CPU idle for A0 chip since the HW does not support it */
845 if (is_soc_rev(CHIP_REV_1_0)) {
846 static const char * const nodes_path[] = {
847 "/cpus/cpu@0",
848 "/cpus/cpu@1",
849 "/cpus/cpu@2",
850 "/cpus/cpu@3",
851 };
852
853 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
854 nodeoff = fdt_path_offset(blob, nodes_path[i]);
855 if (nodeoff < 0)
856 continue; /* Not found, skip it */
857
858 debug("Found %s node\n", nodes_path[i]);
859
860 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
861 if (rc == -FDT_ERR_NOTFOUND)
862 continue;
863 if (rc) {
864 printf("Unable to update property %s:%s, err=%s\n",
865 nodes_path[i], "status", fdt_strerror(rc));
866 return rc;
867 }
868
869 debug("Remove %s:%s\n", nodes_path[i],
870 "cpu-idle-states");
871 }
872 }
873
874 if (is_imx8mql()) {
875 disable_vpu_nodes(blob);
876 if (check_dcss_fused()) {
877 printf("DCSS is fused\n");
878 disable_dcss_nodes(blob);
879 check_mipi_dsi_nodes(blob);
880 }
881 }
882
883 if (is_imx8md())
884 disable_cpu_nodes(blob, 2);
885
886 #elif defined(CONFIG_IMX8MM)
887 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
888 disable_vpu_nodes(blob);
889
890 if (is_imx8mmd() || is_imx8mmdl())
891 disable_cpu_nodes(blob, 2);
892 else if (is_imx8mms() || is_imx8mmsl())
893 disable_cpu_nodes(blob, 3);
894
895 #elif defined(CONFIG_IMX8MN)
896 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
897 disable_gpu_nodes(blob);
898
899 if (is_imx8mnd() || is_imx8mndl())
900 disable_cpu_nodes(blob, 2);
901 else if (is_imx8mns() || is_imx8mnsl())
902 disable_cpu_nodes(blob, 3);
903
904 #elif defined(CONFIG_IMX8MP)
905 if (is_imx8mpl())
906 disable_vpu_nodes(blob);
907
908 if (is_imx8mpl() || is_imx8mp6())
909 disable_npu_nodes(blob);
910
911 if (is_imx8mpl())
912 disable_isp_nodes(blob);
913
914 if (is_imx8mpl() || is_imx8mp6())
915 disable_dsp_nodes(blob);
916
917 if (is_imx8mpd())
918 disable_cpu_nodes(blob, 2);
919 #endif
920
921 return 0;
922 }
923 #endif
924
925 #if !CONFIG_IS_ENABLED(SYSRESET)
reset_cpu(ulong addr)926 void reset_cpu(ulong addr)
927 {
928 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
929
930 /* Clear WDA to trigger WDOG_B immediately */
931 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
932
933 while (1) {
934 /*
935 * spin for .5 seconds before reset
936 */
937 }
938 }
939 #endif
940
941 #if defined(CONFIG_ARCH_MISC_INIT)
acquire_buildinfo(void)942 static void acquire_buildinfo(void)
943 {
944 u64 atf_commit = 0;
945 struct arm_smccc_res res;
946
947 /* Get ARM Trusted Firmware commit id */
948 arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
949 0, 0, 0, 0, 0, 0, &res);
950 atf_commit = res.a0;
951 if (atf_commit == 0xffffffff) {
952 debug("ATF does not support build info\n");
953 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
954 }
955
956 printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
957 }
958
arch_misc_init(void)959 int arch_misc_init(void)
960 {
961 acquire_buildinfo();
962
963 return 0;
964 }
965 #endif
966
imx_tmu_arch_init(void * reg_base)967 void imx_tmu_arch_init(void *reg_base)
968 {
969 if (is_imx8mm() || is_imx8mn()) {
970 /* Load TCALIV and TASR from fuses */
971 struct ocotp_regs *ocotp =
972 (struct ocotp_regs *)OCOTP_BASE_ADDR;
973 struct fuse_bank *bank = &ocotp->bank[3];
974 struct fuse_bank3_regs *fuse =
975 (struct fuse_bank3_regs *)bank->fuse_regs;
976
977 u32 tca_rt, tca_hr, tca_en;
978 u32 buf_vref, buf_slope;
979
980 tca_rt = fuse->ana0 & 0xFF;
981 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
982 tca_en = (fuse->ana0 & 0x2000000) >> 25;
983
984 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
985 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
986
987 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
988 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
989 (ulong)reg_base + 0x30);
990 }
991 #ifdef CONFIG_IMX8MP
992 /* Load TCALIV0/1/m40 and TRIM from fuses */
993 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
994 struct fuse_bank *bank = &ocotp->bank[38];
995 struct fuse_bank38_regs *fuse =
996 (struct fuse_bank38_regs *)bank->fuse_regs;
997 struct fuse_bank *bank2 = &ocotp->bank[39];
998 struct fuse_bank39_regs *fuse2 =
999 (struct fuse_bank39_regs *)bank2->fuse_regs;
1000 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
1001 u32 reg;
1002 u32 tca40[2], tca25[2], tca105[2];
1003
1004 /* For blank sample */
1005 if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
1006 !fuse->ana_trim4 && !fuse2->ana_trim5) {
1007 /* Use a default 25C binary codes */
1008 tca25[0] = 1596;
1009 tca25[1] = 1596;
1010 writel(tca25[0], (ulong)reg_base + 0x30);
1011 writel(tca25[1], (ulong)reg_base + 0x34);
1012 return;
1013 }
1014
1015 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
1016 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1017 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1018 bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1019 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1020 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1021
1022 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
1023 writel(reg, (ulong)reg_base + 0x3c);
1024
1025 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1026 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1027 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1028 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1029 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1030 tca25[1] = fuse2->ana_trim5 & 0xFFF;
1031 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1032
1033 /* use 25c for 1p calibration */
1034 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1035 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1036 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1037 #endif
1038 }
1039
1040 #if defined(CONFIG_SPL_BUILD)
1041 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1042 bool serror_need_skip = true;
1043
do_error(struct pt_regs * pt_regs,unsigned int esr)1044 void do_error(struct pt_regs *pt_regs, unsigned int esr)
1045 {
1046 /*
1047 * If stack is still in ROM reserved OCRAM not switch to SPL,
1048 * it is the ROM SError
1049 */
1050 ulong sp;
1051
1052 asm volatile("mov %0, sp" : "=r"(sp) : );
1053
1054 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1055 /* Check for ERR050342, imx8mq HDCP enabled parts */
1056 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1057 serror_need_skip = false;
1058 return; /* Do nothing skip the SError in ROM */
1059 }
1060
1061 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1062 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1063 serror_need_skip = false;
1064 return; /* Do nothing skip the SError in ROM */
1065 }
1066 }
1067
1068 efi_restore_gd();
1069 printf("\"Error\" handler, esr 0x%08x\n", esr);
1070 show_regs(pt_regs);
1071 panic("Resetting CPU ...\n");
1072 }
1073 #endif
1074 #endif
1075
1076 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
env_get_location(enum env_operation op,int prio)1077 enum env_location env_get_location(enum env_operation op, int prio)
1078 {
1079 enum boot_device dev = get_boot_device();
1080 enum env_location env_loc = ENVL_UNKNOWN;
1081
1082 if (prio)
1083 return env_loc;
1084
1085 switch (dev) {
1086 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1087 case QSPI_BOOT:
1088 env_loc = ENVL_SPI_FLASH;
1089 break;
1090 #endif
1091 #ifdef CONFIG_ENV_IS_IN_NAND
1092 case NAND_BOOT:
1093 env_loc = ENVL_NAND;
1094 break;
1095 #endif
1096 #ifdef CONFIG_ENV_IS_IN_MMC
1097 case SD1_BOOT:
1098 case SD2_BOOT:
1099 case SD3_BOOT:
1100 case MMC1_BOOT:
1101 case MMC2_BOOT:
1102 case MMC3_BOOT:
1103 env_loc = ENVL_MMC;
1104 break;
1105 #endif
1106 default:
1107 #if defined(CONFIG_ENV_IS_NOWHERE)
1108 env_loc = ENVL_NOWHERE;
1109 #endif
1110 break;
1111 }
1112
1113 return env_loc;
1114 }
1115
1116 #ifndef ENV_IS_EMBEDDED
env_get_offset(long long defautl_offset)1117 long long env_get_offset(long long defautl_offset)
1118 {
1119 enum boot_device dev = get_boot_device();
1120
1121 switch (dev) {
1122 case NAND_BOOT:
1123 return (60 << 20); /* 60MB offset for NAND */
1124 default:
1125 break;
1126 }
1127
1128 return defautl_offset;
1129 }
1130 #endif
1131 #endif
1132