1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright 2021 NXP
4  *
5  * Driver for DSPI Controller
6  *
7  */
8 
9 #include <assert.h>
10 #include <drivers/ls_dspi.h>
11 #include <io.h>
12 #include <kernel/boot.h>
13 #include <kernel/delay.h>
14 #include <kernel/dt.h>
15 #include <libfdt.h>
16 #include <mm/core_memprot.h>
17 #include <platform_config.h>
18 #include <util.h>
19 
20 /* SPI register offset */
21 #define DSPI_MCR	0x0 /* Module Configuration Register */
22 #define DSPI_TCR	0x8 /* Transfer Count Register */
23 #define DSPI_CTAR0 \
24 	0xC /* Clock and Transfer Attributes Register (in Master mode) */
25 #define DSPI_CTAR1 \
26 	0x10 /* Clock and Transfer Attributes Register (in Master mode) */
27 #define DSPI_SR     0x2C  /* Status Register */
28 #define DSPI_RSER   0x30  /* DMA/Interrupt Request Select and Enable Register */
29 #define DSPI_PUSHR  0x34  /* PUSH TX FIFO Register In Master Mode */
30 #define DSPI_POPR   0x38  /* POP RX FIFO Register */
31 #define DSPI_TXFR0  0x3C  /* Transmit FIFO Registers */
32 #define DSPI_TXFR1  0x40  /* Transmit FIFO Registers */
33 #define DSPI_TXFR2  0x44  /* Transmit FIFO Registers */
34 #define DSPI_TXFR3  0x48  /* Transmit FIFO Registers */
35 #define DSPI_RXFR0  0x7C  /* Receive FIFO Registers */
36 #define DSPI_RXFR1  0x80  /* Receive FIFO Registers */
37 #define DSPI_RXFR2  0x84  /* Receive FIFO Registers */
38 #define DSPI_RXFR3  0x88  /* Receive FIFO Registers */
39 #define DSPI_CTARE0 0x11C /* Clock and Transfer Attributes Register Extended */
40 #define DSPI_CTARE1 0x120 /* Clock and Transfer Attributes Register Extended */
41 #define DSPI_SREX   0x13C /* Status Register Extended */
42 
43 /* Module configuration */
44 #define DSPI_MCR_MSTR	0x80000000         /* Master/Slave Mode Select [0] */
45 #define DSPI_MCR_CSCK	0x40000000         /* Continuous SCK Enable [1] */
46 #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) /* SPI Configuration [2-3] */
47 #define DSPI_MCR_ROOE	\
48 	0x01000000 /* Receive FIFO Overflow Overwrite Enable[7] */
49 #define DSPI_MCR_PCSIS(x) \
50 	(1 << (16 + (x))) /* Peripheral Chip Select x Inactive State [12-15] */
51 #define DSPI_MCR_PCSIS_MASK (0xff << 16)
52 #define DSPI_MCR_MDIS       0x00004000 /* Module Disable [17] */
53 #define DSPI_MCR_DTXF       0x00002000 /* Disable Transmit FIFO [18] */
54 #define DSPI_MCR_DRXF       0x00001000 /* Disable Receive FIFO [19] */
55 #define DSPI_MCR_CTXF       0x00000800 /* Clear TX FIFO [20] */
56 #define DSPI_MCR_CRXF       0x00000400 /* Clear RX FIFO [21] */
57 #define DPSI_XSPI           0x00000008 /* Extended SPI Mode [28] */
58 #define DSPI_MCR_PES        0x00000002 /* Parity Error Stop [30] */
59 #define DSPI_MCR_HALT       0x00000001 /* Halt [31] */
60 #define DPSI_ENABLE         0x0
61 #define DSPI_DISABLE        0x1
62 
63 /* Transfer count */
64 #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
65 
66 /* Status */
67 #define DSPI_SR_TXRXS    0x40000000               /* TX and RX Status [1] */
68 #define DSPI_SR_TXCTR(x) \
69 	(((x) & 0x0000F000) >> 12) /* TX FIFO Counter [16-19] */
70 #define DSPI_SR_RXCTR(x) \
71 	(((x) & 0x000000F0) >> 4)  /* RX FIFO Counter [24-27] */
72 
73 #define DSPI_DATA_8BIT  SHIFT_U32(8, 0)
74 #define DSPI_DATA_16BIT SHIFT_U32(0xF, 0)
75 
76 #define DSPI_TFR_CONT    (0x80000000)
77 #define DSPI_TFR_CTAS(x) (((x) & 0x07) << 12)
78 #define DSPI_TFR_PCS(x)  (((1 << (x)) & 0x0000003f) << 16)
79 #define DSPI_IDLE_DATA   0x0
80 
81 /* tx/rx data wait timeout value, unit: us */
82 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
83 
84 /* Transfer Fifo */
85 #define DSPI_TFR_TXDATA(x) (((x) & 0x0000FFFF))
86 
87 /* Bit definitions and macros for DRFR */
88 #define DSPI_RFR_RXDATA(x) (((x) & 0x0000FFFF))
89 
90 /* CTAR register pre-configure mask */
91 #define DSPI_CTAR_SET_MODE_MASK \
92 	(DSPI_CTAR_FMSZ(15) | DSPI_CTAR_PCS_SCK(3) | DSPI_CTAR_PA_SCK(3) | \
93 	 DSPI_CTAR_P_DT(3) | DSPI_CTAR_CS_SCK(15) | DSPI_CTAR_A_SCK(15) | \
94 	 DSPI_CTAR_A_DT(15))
95 
96 /* SPI mode flags */
97 #define SPI_CPHA      BIT(0) /* clock phase */
98 #define SPI_CPOL      BIT(1) /* clock polarity */
99 #define SPI_CS_HIGH   BIT(2) /* CS active high */
100 #define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
101 #define SPI_CONT      BIT(4) /* Continuous CS mode */
102 
103 /* default SCK frequency, unit: HZ */
104 #define PLATFORM_CLK          650000000
105 #define DSPI_DEFAULT_SCK_FREQ 10000000
106 #define DSPI_CLK_DIV          4 /* prescaler divisor */
107 #define DSPI_CLK              (PLATFORM_CLK / DSPI_CLK_DIV) /* DSPI clock */
108 #define CS_SPEED_MAX_HZ       1000000   /* Slave max speed */
109 
110 /*
111  * Calculate the divide scaler value between expected SCK frequency
112  * and input clk frequency
113  * req_pbr:	pre-scaler value of baud rate for slave
114  * req_br:	scaler value of baud rate for slave
115  * speed_hz:	speed value of slave
116  * clkrate:	clock value of slave
117  */
dspi_convert_hz_to_baud(unsigned int * req_pbr,unsigned int * req_br,unsigned int speed_hz,unsigned int clkrate)118 static TEE_Result dspi_convert_hz_to_baud(unsigned int *req_pbr,
119 					  unsigned int *req_br,
120 					  unsigned int speed_hz,
121 					  unsigned int clkrate)
122 {
123 	/* Valid pre-scaler values for baud rate*/
124 	static const unsigned int pbr_val[4] = { 2, 3, 5, 7 };
125 	/* Valid baud rate scaler values*/
126 	static const unsigned int brs_val[16] = { 2, 4, 6, 8,
127 						16, 32, 64, 128,
128 						256, 512, 1024, 2048,
129 						4096, 8192, 16384, 32768 };
130 	unsigned int tmp_val = 0;
131 	unsigned int curr_val = 0;
132 	unsigned int i = 0;
133 	unsigned int j = 0;
134 
135 	tmp_val = clkrate / speed_hz;
136 
137 	for (i = 0; i < ARRAY_SIZE(pbr_val); i++) {
138 		for (j = 0; j < ARRAY_SIZE(brs_val); j++) {
139 			curr_val = pbr_val[i] * brs_val[j];
140 			if (curr_val >= tmp_val) {
141 				*req_pbr = i;
142 				*req_br = j;
143 				return TEE_SUCCESS;
144 			}
145 		}
146 	}
147 
148 	EMSG("Can not find valid baud rate, speed_hz is %d, ", speed_hz);
149 	EMSG("clkrate is %d, using max prescaler value", clkrate);
150 
151 	return TEE_ERROR_ITEM_NOT_FOUND;
152 }
153 
154 /*
155  * Configure speed of slave
156  * dspi_data:	DSPI controller chip instance
157  * speed:	speed of slave
158  */
dspi_setup_speed(struct ls_dspi_data * dspi_data,unsigned int speed)159 static void dspi_setup_speed(struct ls_dspi_data *dspi_data,
160 			     unsigned int speed)
161 {
162 	TEE_Result status = TEE_ERROR_GENERIC;
163 	unsigned int bus_setup = 0;
164 	unsigned int bus_clock = 0;
165 	unsigned int req_i = 0;
166 	unsigned int req_j = 0;
167 
168 	bus_clock = dspi_data->bus_clk_hz;
169 
170 	DMSG("DSPI set_speed: expected SCK speed %u, bus_clk %u", speed,
171 	     bus_clock);
172 
173 	bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);
174 	bus_setup &= ~(DSPI_CTAR_BRD | DSPI_CTAR_BRP(0x3) | DSPI_CTAR_BR(0xf));
175 
176 	status = dspi_convert_hz_to_baud(&req_i, &req_j, speed, bus_clock);
177 
178 	/* In case of failure scenario with max speed, setting default speed */
179 	if (status == TEE_ERROR_ITEM_NOT_FOUND) {
180 		speed = dspi_data->speed_hz;
181 		status = dspi_convert_hz_to_baud(&req_i, &req_j,
182 						 speed, bus_clock);
183 	}
184 
185 	if (status == TEE_SUCCESS) {
186 		bus_setup |= (DSPI_CTAR_BRP(req_i) | DSPI_CTAR_BR(req_j));
187 		io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);
188 		dspi_data->speed_hz = speed;
189 	} else {
190 		EMSG("Unable to set speed");
191 	}
192 }
193 
194 /*
195  * Transferred data to TX FIFO
196  * dspi_data:	DSPI controller chip instance
197  */
dspi_tx(struct ls_dspi_data * dspi_data,uint32_t ctrl,uint16_t data)198 static void dspi_tx(struct ls_dspi_data *dspi_data, uint32_t ctrl,
199 		    uint16_t data)
200 {
201 	int timeout = DSPI_TXRX_WAIT_TIMEOUT;
202 	uint32_t dspi_val_addr = dspi_data->base + DSPI_PUSHR;
203 	uint32_t dspi_val = ctrl | data;
204 
205 	/* wait for empty entries in TXFIFO or timeout */
206 	while (DSPI_SR_TXCTR(io_read32(dspi_data->base + DSPI_SR)) >= 4 &&
207 	       timeout--)
208 		udelay(1);
209 
210 	if (timeout >= 0)
211 		io_write32(dspi_val_addr, dspi_val);
212 	else
213 		EMSG("waiting timeout!");
214 }
215 
216 /*
217  * Read data from RX FIFO
218  * dspi_data:	DSPI controller chip instance
219  */
dspi_rx(struct ls_dspi_data * dspi_data)220 static uint16_t dspi_rx(struct ls_dspi_data *dspi_data)
221 {
222 	int timeout = DSPI_TXRX_WAIT_TIMEOUT;
223 	uint32_t dspi_val_addr = dspi_data->base + DSPI_POPR;
224 
225 	/* wait for valid entries in RXFIFO or timeout */
226 	while (DSPI_SR_RXCTR(io_read32(dspi_data->base + DSPI_SR)) == 0 &&
227 	       timeout--)
228 		udelay(1);
229 
230 	if (timeout >= 0)
231 		return (uint16_t)DSPI_RFR_RXDATA(io_read32(dspi_val_addr));
232 
233 	EMSG("waiting timeout!");
234 
235 	return 0xFFFF;
236 }
237 
238 /*
239  * Transfer and Receive 8-bit data
240  * chip:	spi_chip instance
241  * wdata:	TX data queue
242  * rdata:	RX data queue
243  * num_pkts:	number of data packets
244  */
ls_dspi_txrx8(struct spi_chip * chip,uint8_t * wdata,uint8_t * rdata,size_t num_pkts)245 static enum spi_result ls_dspi_txrx8(struct spi_chip *chip, uint8_t *wdata,
246 				     uint8_t *rdata, size_t num_pkts)
247 {
248 	uint8_t *spi_rd = NULL;
249 	uint8_t *spi_wr = NULL;
250 	uint32_t ctrl = 0;
251 	struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
252 						  chip);
253 	unsigned int cs = data->slave_cs;
254 
255 	spi_wr = wdata;
256 	spi_rd = rdata;
257 
258 	/*
259 	 * Assert PCSn signals between transfers
260 	 * select which CTAR register and slave to be used for TX
261 	 * CTAS selects which CTAR to be used, here we are using CTAR0
262 	 * PCS (peripheral chip select) is selecting the slave.
263 	 */
264 	ctrl = DSPI_TFR_CTAS(data->ctar_sel) | DSPI_TFR_PCS(cs);
265 	if (data->slave_mode & SPI_CONT)
266 		ctrl |= DSPI_TFR_CONT;
267 
268 	if (data->slave_data_size_bits != 8) {
269 		EMSG("data_size_bits should be 8, not %u",
270 		     data->slave_data_size_bits);
271 		return SPI_ERR_CFG;
272 	}
273 
274 	while (num_pkts) {
275 		if (wdata && rdata) {
276 			dspi_tx(data, ctrl, *spi_wr++);
277 			*spi_rd++ = dspi_rx(data);
278 		} else if (wdata) {
279 			dspi_tx(data, ctrl, *spi_wr++);
280 			dspi_rx(data);
281 		} else if (rdata) {
282 			dspi_tx(data, ctrl, DSPI_IDLE_DATA);
283 			*spi_rd++ = dspi_rx(data);
284 		}
285 		num_pkts = num_pkts - 1;
286 	}
287 
288 	return SPI_OK;
289 }
290 
291 /*
292  * Transfer and Receive 16-bit data
293  * chip:        spi_chip instance
294  * wdata:	TX data queue
295  * rdata:	RX data queue
296  * num_pkts:	number of data packets
297  */
ls_dspi_txrx16(struct spi_chip * chip,uint16_t * wdata,uint16_t * rdata,size_t num_pkts)298 static enum spi_result ls_dspi_txrx16(struct spi_chip *chip, uint16_t *wdata,
299 				      uint16_t *rdata, size_t num_pkts)
300 {
301 	uint32_t ctrl = 0;
302 	uint16_t *spi_rd = NULL;
303 	uint16_t *spi_wr = NULL;
304 	struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
305 						  chip);
306 	unsigned int cs = data->slave_cs;
307 
308 	spi_wr = wdata;
309 	spi_rd = rdata;
310 
311 	/*
312 	 * Assert PCSn signals between transfers
313 	 * select which CTAR register and slave to be used for TX
314 	 * CTAS selects which CTAR to be used, here we are using CTAR0
315 	 * PCS (peripheral chip select) is selecting the slave.
316 	 */
317 	ctrl = DSPI_TFR_CTAS(data->ctar_sel) | DSPI_TFR_PCS(cs);
318 	if (data->slave_mode & SPI_CONT)
319 		ctrl |= DSPI_TFR_CONT;
320 
321 	if (data->slave_data_size_bits != 16) {
322 		EMSG("data_size_bits should be 16, not %u",
323 		     data->slave_data_size_bits);
324 		return SPI_ERR_CFG;
325 	}
326 
327 	while (num_pkts) {
328 		if (wdata && rdata) {
329 			dspi_tx(data, ctrl, *spi_wr++);
330 			*spi_rd++ = dspi_rx(data);
331 		} else if (wdata) {
332 			dspi_tx(data, ctrl, *spi_wr++);
333 			dspi_rx(data);
334 		} else if (rdata) {
335 			dspi_tx(data, ctrl, DSPI_IDLE_DATA);
336 			*spi_rd++ = dspi_rx(data);
337 		}
338 		num_pkts = num_pkts - 1;
339 	}
340 
341 	return SPI_OK;
342 }
343 
344 /*
345  * Statrt DSPI module
346  * chip:	spi_chip instance
347  */
ls_dspi_start(struct spi_chip * chip)348 static void ls_dspi_start(struct spi_chip *chip)
349 {
350 	struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
351 						  chip);
352 
353 	DMSG("Start DSPI Module");
354 	io_clrbits32(data->base + DSPI_MCR, DSPI_MCR_HALT);
355 }
356 
357 /*
358  * Stop DSPI module
359  * chip:	spi_chip instance
360  */
ls_dspi_end(struct spi_chip * chip)361 static void ls_dspi_end(struct spi_chip *chip)
362 {
363 	struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
364 						  chip);
365 
366 	/* De-assert PCSn if in CONT mode */
367 	if (data->slave_mode & SPI_CONT) {
368 		unsigned int cs = data->slave_cs;
369 		unsigned int ctrl = DSPI_TFR_CTAS(data->ctar_sel) |
370 				    DSPI_TFR_PCS(cs);
371 
372 		/* Dummy read to deassert */
373 		dspi_tx(data, ctrl, DSPI_IDLE_DATA);
374 		dspi_rx(data);
375 	}
376 
377 	DMSG("Stop DSPI Module");
378 	io_setbits32(data->base + DSPI_MCR, DSPI_MCR_HALT);
379 }
380 
381 /*
382  * Clear RX and TX FIFO
383  * dspi_data:   DSPI controller chip instance
384  */
dspi_flush_fifo(struct ls_dspi_data * dspi_data)385 void dspi_flush_fifo(struct ls_dspi_data *dspi_data)
386 {
387 	unsigned int mcr_val = 0;
388 
389 	mcr_val = io_read32(dspi_data->base + DSPI_MCR);
390 	/* flush RX and TX FIFO */
391 	mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
392 
393 	io_write32(dspi_data->base + DSPI_MCR, mcr_val);
394 }
395 
396 /*
397  * Configure active state of slave
398  * dspi_data:   DSPI controller chip instance
399  * cs:		chip select value of slave
400  * state:	slave mode
401  */
dspi_set_cs_active_state(struct ls_dspi_data * dspi_data,unsigned int cs,unsigned int state)402 static void dspi_set_cs_active_state(struct ls_dspi_data *dspi_data,
403 				     unsigned int cs, unsigned int state)
404 {
405 	DMSG("Set CS active state cs=%d state=%d", cs, state);
406 
407 	if (state & SPI_CS_HIGH)
408 		/* CSx inactive state is low */
409 		io_clrbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));
410 	else
411 		/* CSx inactive state is high */
412 		io_setbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));
413 }
414 
415 /*
416  * Configure transfer state of slave
417  * dspi_data:   DSPI controller chip instance
418  * state:	slave mode
419  */
dspi_set_transfer_state(struct ls_dspi_data * dspi_data,unsigned int state)420 static void dspi_set_transfer_state(struct ls_dspi_data *dspi_data,
421 				    unsigned int state)
422 {
423 	unsigned int bus_setup = 0;
424 
425 	DMSG("Set transfer state=%d bits=%d", state,
426 	     dspi_data->slave_data_size_bits);
427 
428 	bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);
429 	bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
430 	bus_setup |= dspi_data->ctar_val;
431 	bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
432 
433 	if (state & SPI_CPOL)
434 		bus_setup |= DSPI_CTAR_CPOL;
435 	if (state & SPI_CPHA)
436 		bus_setup |= DSPI_CTAR_CPHA;
437 	if (state & SPI_LSB_FIRST)
438 		bus_setup |= DSPI_CTAR_LSBFE;
439 
440 	if (dspi_data->slave_data_size_bits == 8)
441 		bus_setup |= DSPI_CTAR_FMSZ(7);
442 	else if (dspi_data->slave_data_size_bits == 16)
443 		bus_setup |= DSPI_CTAR_FMSZ(15);
444 
445 	if (dspi_data->ctar_sel == 0)
446 		io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);
447 	else
448 		io_write32(dspi_data->base + DSPI_CTAR1, bus_setup);
449 }
450 
451 /*
452  * Configure speed of slave
453  * dspi_data:   DSPI controller chip instance
454  * speed_max_hz:        maximum speed for slave
455  */
dspi_set_speed(struct ls_dspi_data * dspi_data,unsigned int speed_max_hz)456 static void dspi_set_speed(struct ls_dspi_data *dspi_data,
457 			   unsigned int speed_max_hz)
458 {
459 	dspi_setup_speed(dspi_data, speed_max_hz);
460 }
461 
462 /*
463  * Configure slave for DSPI controller
464  * dspi_data:		DSPI controller chip instance
465  * cs:			chip select value of slave
466  * speed_max_hz:	maximum speed of slave
467  * state:		slave mode
468  */
dspi_config_slave_state(struct ls_dspi_data * dspi_data,unsigned int cs,unsigned int speed_max_hz,unsigned int state)469 static void dspi_config_slave_state(struct ls_dspi_data *dspi_data,
470 				    unsigned int cs, unsigned int speed_max_hz,
471 				    unsigned int state)
472 {
473 	unsigned int sr_val = 0;
474 
475 	/* configure speed */
476 	dspi_set_speed(dspi_data, speed_max_hz);
477 
478 	/* configure transfer state */
479 	dspi_set_transfer_state(dspi_data, state);
480 
481 	/* configure active state of CSX */
482 	dspi_set_cs_active_state(dspi_data, cs, state);
483 
484 	/* clear FIFO */
485 	dspi_flush_fifo(dspi_data);
486 
487 	/* check module TX and RX status */
488 	sr_val = io_read32(dspi_data->base + DSPI_SR);
489 	if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
490 		EMSG("DSPI RX/TX not ready");
491 }
492 
493 /*
494  * Configure master for DSPI controller
495  * dspi_data: DSPI controller chip instance
496  * mcr_val: value of master configuration register
497  */
dspi_set_master_state(struct ls_dspi_data * dspi_data,unsigned int mcr_val)498 static void dspi_set_master_state(struct ls_dspi_data *dspi_data,
499 				  unsigned int mcr_val)
500 {
501 	DMSG("Set master state val=0x%x", mcr_val);
502 	io_write32(dspi_data->base + DSPI_MCR, mcr_val);
503 }
504 
505 /*
506  * Configure DSPI controller
507  * chip: spi_chip instance
508  */
ls_dspi_configure(struct spi_chip * chip)509 static void ls_dspi_configure(struct spi_chip *chip)
510 {
511 	struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
512 						  chip);
513 	unsigned int mcr_cfg_val = 0;
514 
515 	mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | DSPI_MCR_CRXF |
516 		      DSPI_MCR_CTXF;
517 
518 	/* Configure Master */
519 	dspi_set_master_state(data, mcr_cfg_val);
520 
521 	/* Configure DSPI slave */
522 	dspi_config_slave_state(data, data->slave_cs, data->slave_speed_max_hz,
523 				data->slave_mode);
524 }
525 
526 /*
527  * Extract information for DSPI Controller from the DTB
528  * dspi_data: DSPI controller chip instance
529  */
get_info_from_device_tree(struct ls_dspi_data * dspi_data)530 static TEE_Result get_info_from_device_tree(struct ls_dspi_data *dspi_data)
531 {
532 	const fdt32_t *bus_num = NULL;
533 	const fdt32_t *chip_select_num = NULL;
534 	size_t size = 0;
535 	int node = 0;
536 	vaddr_t ctrl_base = 0;
537 	void *fdt = NULL;
538 
539 	/*
540 	 * First get the DSPI Controller base address from the DTB
541 	 * if DTB present and if the DSPI Controller defined in it.
542 	 */
543 	fdt = get_dt();
544 	if (!fdt) {
545 		EMSG("Unable to get DTB, DSPI init failed\n");
546 		return TEE_ERROR_ITEM_NOT_FOUND;
547 	}
548 
549 	node = 0;
550 	while (node != -FDT_ERR_NOTFOUND) {
551 		node = fdt_node_offset_by_compatible(fdt, node,
552 						     "fsl,lx2160a-dspi");
553 		if (!(_fdt_get_status(fdt, node) & DT_STATUS_OK_SEC))
554 			continue;
555 
556 		bus_num = fdt_getprop(fdt, node, "bus-num", NULL);
557 		if (bus_num && dspi_data->slave_bus ==
558 			(unsigned int)fdt32_to_cpu(*bus_num)) {
559 			if (dt_map_dev(fdt, node, &ctrl_base, &size) < 0) {
560 				EMSG("Unable to get virtual address");
561 				return TEE_ERROR_GENERIC;
562 			}
563 			break;
564 		}
565 	}
566 
567 	dspi_data->base = ctrl_base;
568 	dspi_data->bus_clk_hz = DSPI_CLK;
569 
570 	chip_select_num = fdt_getprop(fdt, node, "spi-num-chipselects", NULL);
571 	if (chip_select_num)
572 		dspi_data->num_chipselect = (int)fdt32_to_cpu(*chip_select_num);
573 	else
574 		return TEE_ERROR_ITEM_NOT_FOUND;
575 
576 	dspi_data->speed_hz = DSPI_DEFAULT_SCK_FREQ;
577 
578 	return TEE_SUCCESS;
579 }
580 
581 static const struct spi_ops ls_dspi_ops = {
582 	.configure = ls_dspi_configure,
583 	.start = ls_dspi_start,
584 	.txrx8 = ls_dspi_txrx8,
585 	.txrx16 = ls_dspi_txrx16,
586 	.end = ls_dspi_end,
587 };
588 DECLARE_KEEP_PAGER(ls_dspi_ops);
589 
ls_dspi_init(struct ls_dspi_data * dspi_data)590 TEE_Result ls_dspi_init(struct ls_dspi_data *dspi_data)
591 {
592 	TEE_Result status = TEE_ERROR_GENERIC;
593 
594 	/*
595 	 * First get the DSPI Controller base address from the DTB,
596 	 * if DTB present and if the DSPI Controller defined in it.
597 	 */
598 	if (dspi_data)
599 		status = get_info_from_device_tree(dspi_data);
600 	if (status == TEE_SUCCESS)
601 		/* generic DSPI chip handle */
602 		dspi_data->chip.ops = &ls_dspi_ops;
603 	else
604 		EMSG("Unable to get info from device tree");
605 
606 	return status;
607 }
608