1 /*
2 * Adapted for Motorola MPC8560 chips
3 * Xianghua Xiao <x.xiao@motorola.com>
4 *
5 * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
6 * copyright notice:
7 *
8 * General Purpose functions for the global management of the
9 * 8220 Communication Processor Module.
10 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
12 * 2.3.99 Updates
13 * Copyright (c) 2003 Motorola,Inc.
14 *
15 * In addition to the individual control of the communication
16 * channels, there are a few functions that globally affect the
17 * communication processor.
18 *
19 * Buffer descriptors must be allocated from the dual ported memory
20 * space. The allocator for that is here. When the communication
21 * process is reset, we reclaim the memory available. There is
22 * currently no deallocator for this memory.
23 */
24 #include <common.h>
25 #include <asm-offsets.h>
26 #include <asm/cpm_85xx.h>
27 #include <asm/global_data.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /*
32 * because we have stack and init data in dual port ram
33 * we must reduce the size
34 */
35 #undef CPM_DATAONLY_SIZE
36 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
37
38 void
m8560_cpm_reset(void)39 m8560_cpm_reset(void)
40 {
41 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
42 volatile ulong count;
43
44 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
45
46 /* Reclaim the DP memory for our use.
47 */
48 gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
49 gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
50
51 /*
52 * Reset CPM
53 */
54 cpm->im_cpm_cp.cpcr = CPM_CR_RST;
55 count = 0;
56 do { /* Spin until command processed */
57 __asm__ __volatile__ ("eieio");
58 } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
59 }
60
61 /* Allocate some memory from the dual ported ram.
62 * To help protocols with object alignment restrictions, we do that
63 * if they ask.
64 */
65 uint
m8560_cpm_dpalloc(uint size,uint align)66 m8560_cpm_dpalloc(uint size, uint align)
67 {
68 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
69 uint retloc;
70 uint align_mask, off;
71 uint savebase;
72
73 align_mask = align - 1;
74 savebase = gd->arch.dp_alloc_base;
75
76 off = gd->arch.dp_alloc_base & align_mask;
77 if (off != 0)
78 gd->arch.dp_alloc_base += (align - off);
79
80 if ((off = size & align_mask) != 0)
81 size += align - off;
82
83 if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
84 gd->arch.dp_alloc_base = savebase;
85 panic("m8560_cpm_dpalloc: ran out of dual port ram!");
86 }
87
88 retloc = gd->arch.dp_alloc_base;
89 gd->arch.dp_alloc_base += size;
90
91 memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
92
93 return(retloc);
94 }
95
96 /* We also own one page of host buffer space for the allocation of
97 * UART "fifos" and the like.
98 */
99 uint
m8560_cpm_hostalloc(uint size,uint align)100 m8560_cpm_hostalloc(uint size, uint align)
101 {
102 /* the host might not even have RAM yet - just use dual port RAM */
103 return (m8560_cpm_dpalloc(size, align));
104 }
105
106 /* Set a baud rate generator. This needs lots of work. There are
107 * eight BRGs, which can be connected to the CPM channels or output
108 * as clocks. The BRGs are in two different block of internal
109 * memory mapped space.
110 * The baud rate clock is the system clock divided by something.
111 * It was set up long ago during the initial boot phase and is
112 * is given to us.
113 * Baud rate clocks are zero-based in the driver code (as that maps
114 * to port numbers). Documentation uses 1-based numbering.
115 */
116 #define BRG_INT_CLK gd->arch.brg_clk
117 #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
118
119 /* This function is used by UARTS, or anything else that uses a 16x
120 * oversampled clock.
121 */
122 void
m8560_cpm_setbrg(uint brg,uint rate)123 m8560_cpm_setbrg(uint brg, uint rate)
124 {
125 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
126 volatile uint *bp;
127
128 /* This is good enough to get SMCs running.....
129 */
130 if (brg < 4) {
131 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
132 }
133 else {
134 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
135 brg -= 4;
136 }
137 bp += brg;
138 *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
139 }
140
141 /* This function is used to set high speed synchronous baud rate
142 * clocks.
143 */
144 void
m8560_cpm_fastbrg(uint brg,uint rate,int div16)145 m8560_cpm_fastbrg(uint brg, uint rate, int div16)
146 {
147 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
148 volatile uint *bp;
149
150 /* This is good enough to get SMCs running.....
151 */
152 if (brg < 4) {
153 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
154 }
155 else {
156 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
157 brg -= 4;
158 }
159 bp += brg;
160 *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
161 if (div16)
162 *bp |= CPM_BRG_DIV16;
163 }
164
165 /* This function is used to set baud rate generators using an external
166 * clock source and 16x oversampling.
167 */
168
169 void
m8560_cpm_extcbrg(uint brg,uint rate,uint extclk,int pinsel)170 m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
171 {
172 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
173 volatile uint *bp;
174
175 if (brg < 4) {
176 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
177 }
178 else {
179 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
180 brg -= 4;
181 }
182 bp += brg;
183 *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
184 if (pinsel == 0)
185 *bp |= CPM_BRG_EXTC_CLK3_9;
186 else
187 *bp |= CPM_BRG_EXTC_CLK5_15;
188 }
189