1 /*
2  * Copyright (C) 2018 Marvell International Ltd.
3  *
4  * SPDX-License-Identifier:     BSD-3-Clause
5  * https://spdx.org/licenses
6  */
7 
8 #include <platform_def.h>
9 
10 #include <bl1/bl1.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/sp805.h>
14 #include <drivers/console.h>
15 #include <plat/common/platform.h>
16 
17 #include <plat_marvell.h>
18 
19 /* Weak definitions may be overridden in specific Marvell standard platform */
20 #pragma weak bl1_early_platform_setup
21 #pragma weak bl1_plat_arch_setup
22 #pragma weak bl1_platform_setup
23 #pragma weak bl1_plat_sec_mem_layout
24 
25 /* Data structure which holds the extents of the RAM for BL1*/
26 static meminfo_t bl1_ram_layout;
27 
bl1_plat_sec_mem_layout(void)28 meminfo_t *bl1_plat_sec_mem_layout(void)
29 {
30 	return &bl1_ram_layout;
31 }
32 
33 /*
34  * BL1 specific platform actions shared between Marvell standard platforms.
35  */
marvell_bl1_early_platform_setup(void)36 void marvell_bl1_early_platform_setup(void)
37 {
38 	/* Initialize the console to provide early debug support */
39 	marvell_console_boot_init();
40 
41 	/* Allow BL1 to see the whole Trusted RAM */
42 	bl1_ram_layout.total_base = MARVELL_BL_RAM_BASE;
43 	bl1_ram_layout.total_size = MARVELL_BL_RAM_SIZE;
44 }
45 
bl1_early_platform_setup(void)46 void bl1_early_platform_setup(void)
47 {
48 	marvell_bl1_early_platform_setup();
49 }
50 
51 /*
52  * Perform the very early platform specific architecture setup shared between
53  * MARVELL standard platforms. This only does basic initialization. Later
54  * architectural setup (bl1_arch_setup()) does not do anything platform
55  * specific.
56  */
marvell_bl1_plat_arch_setup(void)57 void marvell_bl1_plat_arch_setup(void)
58 {
59 	marvell_setup_page_tables(bl1_ram_layout.total_base,
60 				  bl1_ram_layout.total_size,
61 				  BL1_RO_BASE,
62 				  BL1_RO_LIMIT,
63 				  BL1_RO_DATA_BASE,
64 				  BL1_RO_DATA_END
65 #if USE_COHERENT_MEM
66 				, BL_COHERENT_RAM_BASE,
67 				  BL_COHERENT_RAM_END
68 #endif
69 				);
70 	enable_mmu_el3(0);
71 }
72 
bl1_plat_arch_setup(void)73 void bl1_plat_arch_setup(void)
74 {
75 	marvell_bl1_plat_arch_setup();
76 }
77 
78 /*
79  * Perform the platform specific architecture setup shared between
80  * MARVELL standard platforms.
81  */
marvell_bl1_platform_setup(void)82 void marvell_bl1_platform_setup(void)
83 {
84 	/* Initialise the IO layer and register platform IO devices */
85 	plat_marvell_io_setup();
86 }
87 
bl1_platform_setup(void)88 void bl1_platform_setup(void)
89 {
90 	marvell_bl1_platform_setup();
91 }
92 
bl1_plat_prepare_exit(entry_point_info_t * ep_info)93 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
94 {
95 #ifdef EL3_PAYLOAD_BASE
96 	/*
97 	 * Program the EL3 payload's entry point address into the CPUs mailbox
98 	 * in order to release secondary CPUs from their holding pen and make
99 	 * them jump there.
100 	 */
101 	marvell_program_trusted_mailbox(ep_info->pc);
102 	dsbsy();
103 	sev();
104 #endif
105 }
106