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Searched defs:mdiv (Results 1 – 11 of 11) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c44 u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; in cm_basic_init() local
201 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
232 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
/u-boot/drivers/clk/exynos/
A Dclk-pll.c22 unsigned long mdiv, sdiv, pdiv; in pll145x_get_rate() local
/u-boot/drivers/clk/imx/
A Dclk-pll14xx.c72 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
89 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll1443x_recalc_rate() local
A Dclk.h32 unsigned int mdiv; member
/u-boot/drivers/clk/altera/
A Dclk-agilex.c204 u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib; in calc_vocalib_pll() local
349 u64 fref, arefdiv, mdiv, reg, vco; in clk_get_vco_clk_hz() local
/u-boot/drivers/i2c/
A Docteon_i2c.c616 int ndiv, mdiv; in twsi_calc_div() local
/u-boot/board/samsung/trats/
A Dsetup.h229 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
/u-boot/arch/arm/mach-exynos/
A Dexynos4_setup.h340 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
A Dexynos5_setup.h22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) argument
/u-boot/arch/arm/include/asm/arch-tegra/
A Dbpmp_abi.h1367 uint16_t mdiv; /**< input divider value */ member
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mm.h40 int mdiv; member

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