1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #ifndef __MDP5_KMS_H__
8 #define __MDP5_KMS_H__
9
10 #include "msm_drv.h"
11 #include "msm_kms.h"
12 #include "disp/mdp_kms.h"
13 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
14 #include "mdp5.xml.h"
15 #include "mdp5_pipe.h"
16 #include "mdp5_mixer.h"
17 #include "mdp5_ctl.h"
18 #include "mdp5_smp.h"
19
20 struct mdp5_kms {
21 struct mdp_kms base;
22
23 struct drm_device *dev;
24
25 struct platform_device *pdev;
26
27 unsigned num_hwpipes;
28 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
29
30 unsigned num_hwmixers;
31 struct mdp5_hw_mixer *hwmixers[8];
32
33 unsigned num_intfs;
34 struct mdp5_interface *intfs[5];
35
36 struct mdp5_cfg_handler *cfg;
37 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
38
39 /*
40 * Global private object state, Do not access directly, use
41 * mdp5_global_get_state()
42 */
43 struct drm_modeset_lock glob_state_lock;
44 struct drm_private_obj glob_state;
45
46 struct mdp5_smp *smp;
47 struct mdp5_ctl_manager *ctlm;
48
49 /* io/register spaces: */
50 void __iomem *mmio;
51
52 struct clk *axi_clk;
53 struct clk *ahb_clk;
54 struct clk *core_clk;
55 struct clk *lut_clk;
56 struct clk *tbu_clk;
57 struct clk *tbu_rt_clk;
58 struct clk *vsync_clk;
59
60 /*
61 * lock to protect access to global resources: ie., following register:
62 * - REG_MDP5_DISP_INTF_SEL
63 */
64 spinlock_t resource_lock;
65
66 bool rpm_enabled;
67
68 struct mdp_irq error_handler;
69
70 int enable_count;
71 };
72 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
73
74 /* Global private object state for tracking resources that are shared across
75 * multiple kms objects (planes/crtcs/etc).
76 */
77 #define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)
78 struct mdp5_global_state {
79 struct drm_private_state base;
80
81 struct drm_atomic_state *state;
82 struct mdp5_kms *mdp5_kms;
83
84 struct mdp5_hw_pipe_state hwpipe;
85 struct mdp5_hw_mixer_state hwmixer;
86 struct mdp5_smp_state smp;
87 };
88
89 struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
90 struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s);
91
92 /* Atomic plane state. Subclasses the base drm_plane_state in order to
93 * track assigned hwpipe and hw specific state.
94 */
95 struct mdp5_plane_state {
96 struct drm_plane_state base;
97
98 struct mdp5_hw_pipe *hwpipe;
99 struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */
100
101 /* assigned by crtc blender */
102 enum mdp_mixer_stage_id stage;
103 };
104 #define to_mdp5_plane_state(x) \
105 container_of(x, struct mdp5_plane_state, base)
106
107 struct mdp5_pipeline {
108 struct mdp5_interface *intf;
109 struct mdp5_hw_mixer *mixer;
110 struct mdp5_hw_mixer *r_mixer; /* right mixer */
111 };
112
113 struct mdp5_crtc_state {
114 struct drm_crtc_state base;
115
116 struct mdp5_ctl *ctl;
117 struct mdp5_pipeline pipeline;
118
119 /* these are derivatives of intf/mixer state in mdp5_pipeline */
120 u32 vblank_irqmask;
121 u32 err_irqmask;
122 u32 pp_done_irqmask;
123
124 bool cmd_mode;
125
126 /* should we not write CTL[n].START register on flush? If the
127 * encoder has changed this is set to true, since encoder->enable()
128 * is called after crtc state is committed, but we only want to
129 * write the CTL[n].START register once. This lets us defer
130 * writing CTL[n].START until encoder->enable()
131 */
132 bool defer_start;
133 };
134 #define to_mdp5_crtc_state(x) \
135 container_of(x, struct mdp5_crtc_state, base)
136
137 enum mdp5_intf_mode {
138 MDP5_INTF_MODE_NONE = 0,
139
140 /* Modes used for DSI interface (INTF_DSI type): */
141 MDP5_INTF_DSI_MODE_VIDEO,
142 MDP5_INTF_DSI_MODE_COMMAND,
143
144 /* Modes used for WB interface (INTF_WB type): */
145 MDP5_INTF_WB_MODE_BLOCK,
146 MDP5_INTF_WB_MODE_LINE,
147 };
148
149 struct mdp5_interface {
150 int idx;
151 int num; /* display interface number */
152 enum mdp5_intf_type type;
153 enum mdp5_intf_mode mode;
154 };
155
156 struct mdp5_encoder {
157 struct drm_encoder base;
158 spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */
159 bool enabled;
160 uint32_t bsc;
161
162 struct mdp5_interface *intf;
163 struct mdp5_ctl *ctl;
164 };
165 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
166
mdp5_write(struct mdp5_kms * mdp5_kms,u32 reg,u32 data)167 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
168 {
169 WARN_ON(mdp5_kms->enable_count <= 0);
170 msm_writel(data, mdp5_kms->mmio + reg);
171 }
172
mdp5_read(struct mdp5_kms * mdp5_kms,u32 reg)173 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
174 {
175 WARN_ON(mdp5_kms->enable_count <= 0);
176 return msm_readl(mdp5_kms->mmio + reg);
177 }
178
stage2name(enum mdp_mixer_stage_id stage)179 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
180 {
181 static const char *names[] = {
182 #define NAME(n) [n] = #n
183 NAME(STAGE_UNUSED), NAME(STAGE_BASE),
184 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
185 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
186 #undef NAME
187 };
188 return names[stage];
189 }
190
pipe2name(enum mdp5_pipe pipe)191 static inline const char *pipe2name(enum mdp5_pipe pipe)
192 {
193 static const char *names[] = {
194 #define NAME(n) [SSPP_ ## n] = #n
195 NAME(VIG0), NAME(VIG1), NAME(VIG2),
196 NAME(RGB0), NAME(RGB1), NAME(RGB2),
197 NAME(DMA0), NAME(DMA1),
198 NAME(VIG3), NAME(RGB3),
199 NAME(CURSOR0), NAME(CURSOR1),
200 #undef NAME
201 };
202 return names[pipe];
203 }
204
pipe2nclients(enum mdp5_pipe pipe)205 static inline int pipe2nclients(enum mdp5_pipe pipe)
206 {
207 switch (pipe) {
208 case SSPP_RGB0:
209 case SSPP_RGB1:
210 case SSPP_RGB2:
211 case SSPP_RGB3:
212 return 1;
213 default:
214 return 3;
215 }
216 }
217
intf2err(int intf_num)218 static inline uint32_t intf2err(int intf_num)
219 {
220 switch (intf_num) {
221 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
222 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
223 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
224 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
225 default: return 0;
226 }
227 }
228
intf2vblank(struct mdp5_hw_mixer * mixer,struct mdp5_interface * intf)229 static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,
230 struct mdp5_interface *intf)
231 {
232 /*
233 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
234 * acts as a Vblank signal. The Ping Pong buffer used is bound to
235 * layer mixer.
236 */
237
238 if ((intf->type == INTF_DSI) &&
239 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
240 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;
241
242 if (intf->type == INTF_WB)
243 return MDP5_IRQ_WB_2_DONE;
244
245 switch (intf->num) {
246 case 0: return MDP5_IRQ_INTF0_VSYNC;
247 case 1: return MDP5_IRQ_INTF1_VSYNC;
248 case 2: return MDP5_IRQ_INTF2_VSYNC;
249 case 3: return MDP5_IRQ_INTF3_VSYNC;
250 default: return 0;
251 }
252 }
253
lm2ppdone(struct mdp5_hw_mixer * mixer)254 static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)
255 {
256 return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;
257 }
258
259 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
260 uint32_t old_irqmask);
261 void mdp5_irq_preinstall(struct msm_kms *kms);
262 int mdp5_irq_postinstall(struct msm_kms *kms);
263 void mdp5_irq_uninstall(struct msm_kms *kms);
264 irqreturn_t mdp5_irq(struct msm_kms *kms);
265 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
266 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
267 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
268 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
269
270 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
271 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
272 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
273 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
274 enum drm_plane_type type);
275
276 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
277 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
278
279 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
280 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
281 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
282 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
283 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
284 struct drm_plane *plane,
285 struct drm_plane *cursor_plane, int id);
286
287 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
288 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
289 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
290 struct drm_encoder *slave_encoder);
291 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
292 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
293 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
294
295 #ifdef CONFIG_DRM_MSM_DSI
296 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
297 struct drm_display_mode *mode,
298 struct drm_display_mode *adjusted_mode);
299 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
300 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
301 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
302 struct drm_encoder *slave_encoder);
303 #else
mdp5_cmd_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)304 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
305 struct drm_display_mode *mode,
306 struct drm_display_mode *adjusted_mode)
307 {
308 }
mdp5_cmd_encoder_disable(struct drm_encoder * encoder)309 static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
310 {
311 }
mdp5_cmd_encoder_enable(struct drm_encoder * encoder)312 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
313 {
314 }
mdp5_cmd_encoder_set_split_display(struct drm_encoder * encoder,struct drm_encoder * slave_encoder)315 static inline int mdp5_cmd_encoder_set_split_display(
316 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
317 {
318 return -EINVAL;
319 }
320 #endif
321
322 #endif /* __MDP5_KMS_H__ */
323