1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3
4 #include <linux/mlx5/driver.h>
5 #include "lib/tout.h"
6
7 struct mlx5_timeouts {
8 u64 to[MAX_TIMEOUT_TYPES];
9 };
10
11 static const u32 tout_def_sw_val[MAX_TIMEOUT_TYPES] = {
12 [MLX5_TO_FW_PRE_INIT_TIMEOUT_MS] = 120000,
13 [MLX5_TO_FW_PRE_INIT_WARN_MESSAGE_INTERVAL_MS] = 20000,
14 [MLX5_TO_FW_PRE_INIT_WAIT_MS] = 2,
15 [MLX5_TO_FW_INIT_MS] = 2000,
16 [MLX5_TO_CMD_MS] = 60000,
17 [MLX5_TO_PCI_TOGGLE_MS] = 2000,
18 [MLX5_TO_HEALTH_POLL_INTERVAL_MS] = 2000,
19 [MLX5_TO_FULL_CRDUMP_MS] = 60000,
20 [MLX5_TO_FW_RESET_MS] = 60000,
21 [MLX5_TO_FLUSH_ON_ERROR_MS] = 2000,
22 [MLX5_TO_PCI_SYNC_UPDATE_MS] = 5000,
23 [MLX5_TO_TEARDOWN_MS] = 3000,
24 [MLX5_TO_FSM_REACTIVATE_MS] = 5000,
25 [MLX5_TO_RECLAIM_PAGES_MS] = 5000,
26 [MLX5_TO_RECLAIM_VFS_PAGES_MS] = 120000
27 };
28
tout_set(struct mlx5_core_dev * dev,u64 val,enum mlx5_timeouts_types type)29 static void tout_set(struct mlx5_core_dev *dev, u64 val, enum mlx5_timeouts_types type)
30 {
31 dev->timeouts->to[type] = val;
32 }
33
mlx5_tout_set_def_val(struct mlx5_core_dev * dev)34 void mlx5_tout_set_def_val(struct mlx5_core_dev *dev)
35 {
36 int i;
37
38 for (i = 0; i < MAX_TIMEOUT_TYPES; i++)
39 tout_set(dev, tout_def_sw_val[i], i);
40 }
41
mlx5_tout_init(struct mlx5_core_dev * dev)42 int mlx5_tout_init(struct mlx5_core_dev *dev)
43 {
44 dev->timeouts = kmalloc(sizeof(*dev->timeouts), GFP_KERNEL);
45 if (!dev->timeouts)
46 return -ENOMEM;
47
48 return 0;
49 }
50
mlx5_tout_cleanup(struct mlx5_core_dev * dev)51 void mlx5_tout_cleanup(struct mlx5_core_dev *dev)
52 {
53 kfree(dev->timeouts);
54 }
55
56 /* Time register consists of two fields to_multiplier(time out multiplier)
57 * and to_value(time out value). to_value is the quantity of the time units and
58 * to_multiplier is the type and should be one off these four values.
59 * 0x0: millisecond
60 * 0x1: seconds
61 * 0x2: minutes
62 * 0x3: hours
63 * this function converts the time stored in the two register fields into
64 * millisecond.
65 */
tout_convert_reg_field_to_ms(u32 to_mul,u32 to_val)66 static u64 tout_convert_reg_field_to_ms(u32 to_mul, u32 to_val)
67 {
68 u64 msec = to_val;
69
70 to_mul &= 0x3;
71 /* convert hours/minutes/seconds to miliseconds */
72 if (to_mul)
73 msec *= 1000 * int_pow(60, to_mul - 1);
74
75 return msec;
76 }
77
tout_convert_iseg_to_ms(u32 iseg_to)78 static u64 tout_convert_iseg_to_ms(u32 iseg_to)
79 {
80 return tout_convert_reg_field_to_ms(iseg_to >> 29, iseg_to & 0xfffff);
81 }
82
tout_is_supported(struct mlx5_core_dev * dev)83 static bool tout_is_supported(struct mlx5_core_dev *dev)
84 {
85 return !!ioread32be(&dev->iseg->cmd_q_init_to);
86 }
87
mlx5_tout_query_iseg(struct mlx5_core_dev * dev)88 void mlx5_tout_query_iseg(struct mlx5_core_dev *dev)
89 {
90 u32 to;
91
92 if (!tout_is_supported(dev))
93 return;
94
95 to = ioread32be(&dev->iseg->cmd_q_init_to);
96 tout_set(dev, tout_convert_iseg_to_ms(to), MLX5_TO_FW_INIT_MS);
97
98 to = ioread32be(&dev->iseg->cmd_exec_to);
99 tout_set(dev, tout_convert_iseg_to_ms(to), MLX5_TO_CMD_MS);
100 }
101
_mlx5_tout_ms(struct mlx5_core_dev * dev,enum mlx5_timeouts_types type)102 u64 _mlx5_tout_ms(struct mlx5_core_dev *dev, enum mlx5_timeouts_types type)
103 {
104 return dev->timeouts->to[type];
105 }
106
107 #define MLX5_TIMEOUT_QUERY(fld, reg_out) \
108 ({ \
109 struct mlx5_ifc_default_timeout_bits *time_field; \
110 u32 to_multi, to_value; \
111 u64 to_val_ms; \
112 \
113 time_field = MLX5_ADDR_OF(dtor_reg, reg_out, fld); \
114 to_multi = MLX5_GET(default_timeout, time_field, to_multiplier); \
115 to_value = MLX5_GET(default_timeout, time_field, to_value); \
116 to_val_ms = tout_convert_reg_field_to_ms(to_multi, to_value); \
117 to_val_ms; \
118 })
119
120 #define MLX5_TIMEOUT_FILL(fld, reg_out, dev, to_type, to_extra) \
121 ({ \
122 u64 fw_to = MLX5_TIMEOUT_QUERY(fld, reg_out); \
123 tout_set(dev, fw_to + (to_extra), to_type); \
124 fw_to; \
125 })
126
tout_query_dtor(struct mlx5_core_dev * dev)127 static int tout_query_dtor(struct mlx5_core_dev *dev)
128 {
129 u64 pcie_toggle_to_val, tear_down_to_val;
130 u32 out[MLX5_ST_SZ_DW(dtor_reg)] = {};
131 u32 in[MLX5_ST_SZ_DW(dtor_reg)] = {};
132 int err;
133
134 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_DTOR, 0, 0);
135 if (err)
136 return err;
137
138 pcie_toggle_to_val = MLX5_TIMEOUT_FILL(pcie_toggle_to, out, dev, MLX5_TO_PCI_TOGGLE_MS, 0);
139 MLX5_TIMEOUT_FILL(fw_reset_to, out, dev, MLX5_TO_FW_RESET_MS, pcie_toggle_to_val);
140
141 tear_down_to_val = MLX5_TIMEOUT_FILL(tear_down_to, out, dev, MLX5_TO_TEARDOWN_MS, 0);
142 MLX5_TIMEOUT_FILL(pci_sync_update_to, out, dev, MLX5_TO_PCI_SYNC_UPDATE_MS,
143 tear_down_to_val);
144
145 MLX5_TIMEOUT_FILL(health_poll_to, out, dev, MLX5_TO_HEALTH_POLL_INTERVAL_MS, 0);
146 MLX5_TIMEOUT_FILL(full_crdump_to, out, dev, MLX5_TO_FULL_CRDUMP_MS, 0);
147 MLX5_TIMEOUT_FILL(flush_on_err_to, out, dev, MLX5_TO_FLUSH_ON_ERROR_MS, 0);
148 MLX5_TIMEOUT_FILL(fsm_reactivate_to, out, dev, MLX5_TO_FSM_REACTIVATE_MS, 0);
149 MLX5_TIMEOUT_FILL(reclaim_pages_to, out, dev, MLX5_TO_RECLAIM_PAGES_MS, 0);
150 MLX5_TIMEOUT_FILL(reclaim_vfs_pages_to, out, dev, MLX5_TO_RECLAIM_VFS_PAGES_MS, 0);
151
152 return 0;
153 }
154
mlx5_tout_query_dtor(struct mlx5_core_dev * dev)155 int mlx5_tout_query_dtor(struct mlx5_core_dev *dev)
156 {
157 if (tout_is_supported(dev))
158 return tout_query_dtor(dev);
159
160 return 0;
161 }
162