1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef FSL_MMDC_H 9 #define FSL_MMDC_H 10 11 /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ 12 #define MPWLGCR_HW_WL_EN (1 << 0) 13 14 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ 15 #define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) 16 17 18 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ 19 #define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) 20 21 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ 22 #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) 23 24 /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ 25 #define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 26 27 /* MMDC Core Refresh Control Register (MMDC_MDREF) */ 28 #define MDREF_START_REFRESH (1 << 0) 29 30 /* MMDC Core Special Command Register (MDSCR) */ 31 #define CMD_ADDR_MSB_MR_OP(x) (x << 24) 32 #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) 33 #define MDSCR_DISABLE_CFG_REQ (0 << 15) 34 #define MDSCR_ENABLE_CON_REQ (1 << 15) 35 #define MDSCR_CON_ACK (1 << 14) 36 #define MDSCR_WL_EN (1 << 9) 37 #define CMD_NORMAL (0 << 4) 38 #define CMD_PRECHARGE (1 << 4) 39 #define CMD_AUTO_REFRESH (2 << 4) 40 #define CMD_LOAD_MODE_REG (3 << 4) 41 #define CMD_ZQ_CALIBRATION (4 << 4) 42 #define CMD_PRECHARGE_BANK_OPEN (5 << 4) 43 #define CMD_MRR (6 << 4) 44 #define CMD_BANK_ADDR_0 0x0 45 #define CMD_BANK_ADDR_1 0x1 46 #define CMD_BANK_ADDR_2 0x2 47 #define CMD_BANK_ADDR_3 0x3 48 #define CMD_BANK_ADDR_4 0x4 49 #define CMD_BANK_ADDR_5 0x5 50 #define CMD_BANK_ADDR_6 0x6 51 #define CMD_BANK_ADDR_7 0x7 52 53 /* MMDC Core Control Register (MDCTL) */ 54 #define MDCTL_SDE0 (U(1) << 31) 55 #define MDCTL_SDE1 (1 << 30) 56 57 /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ 58 #define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) 59 60 /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ 61 #define MMDC_MPMUR0_FRC_MSR (1 << 11) 62 63 /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ 64 /* default 64 for a quarter cycle delay */ 65 #define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 66 67 /* MMDC Registers */ 68 struct mmdc_regs { 69 unsigned int mdctl; 70 unsigned int mdpdc; 71 unsigned int mdotc; 72 unsigned int mdcfg0; 73 unsigned int mdcfg1; 74 unsigned int mdcfg2; 75 unsigned int mdmisc; 76 unsigned int mdscr; 77 unsigned int mdref; 78 unsigned int res1[2]; 79 unsigned int mdrwd; 80 unsigned int mdor; 81 unsigned int mdmrr; 82 unsigned int mdcfg3lp; 83 unsigned int mdmr4; 84 unsigned int mdasp; 85 unsigned int res2[239]; 86 unsigned int maarcr; 87 unsigned int mapsr; 88 unsigned int maexidr0; 89 unsigned int maexidr1; 90 unsigned int madpcr0; 91 unsigned int madpcr1; 92 unsigned int madpsr0; 93 unsigned int madpsr1; 94 unsigned int madpsr2; 95 unsigned int madpsr3; 96 unsigned int madpsr4; 97 unsigned int madpsr5; 98 unsigned int masbs0; 99 unsigned int masbs1; 100 unsigned int res3[2]; 101 unsigned int magenp; 102 unsigned int res4[239]; 103 unsigned int mpzqhwctrl; 104 unsigned int mpzqswctrl; 105 unsigned int mpwlgcr; 106 unsigned int mpwldectrl0; 107 unsigned int mpwldectrl1; 108 unsigned int mpwldlst; 109 unsigned int mpodtctrl; 110 unsigned int mprddqby0dl; 111 unsigned int mprddqby1dl; 112 unsigned int mprddqby2dl; 113 unsigned int mprddqby3dl; 114 unsigned int mpwrdqby0dl; 115 unsigned int mpwrdqby1dl; 116 unsigned int mpwrdqby2dl; 117 unsigned int mpwrdqby3dl; 118 unsigned int mpdgctrl0; 119 unsigned int mpdgctrl1; 120 unsigned int mpdgdlst0; 121 unsigned int mprddlctl; 122 unsigned int mprddlst; 123 unsigned int mpwrdlctl; 124 unsigned int mpwrdlst; 125 unsigned int mpsdctrl; 126 unsigned int mpzqlp2ctl; 127 unsigned int mprddlhwctl; 128 unsigned int mpwrdlhwctl; 129 unsigned int mprddlhwst0; 130 unsigned int mprddlhwst1; 131 unsigned int mpwrdlhwst0; 132 unsigned int mpwrdlhwst1; 133 unsigned int mpwlhwerr; 134 unsigned int mpdghwst0; 135 unsigned int mpdghwst1; 136 unsigned int mpdghwst2; 137 unsigned int mpdghwst3; 138 unsigned int mppdcmpr1; 139 unsigned int mppdcmpr2; 140 unsigned int mpswdar0; 141 unsigned int mpswdrdr0; 142 unsigned int mpswdrdr1; 143 unsigned int mpswdrdr2; 144 unsigned int mpswdrdr3; 145 unsigned int mpswdrdr4; 146 unsigned int mpswdrdr5; 147 unsigned int mpswdrdr6; 148 unsigned int mpswdrdr7; 149 unsigned int mpmur0; 150 unsigned int mpwrcadl; 151 unsigned int mpdccr; 152 }; 153 154 struct fsl_mmdc_info { 155 unsigned int mdctl; 156 unsigned int mdpdc; 157 unsigned int mdotc; 158 unsigned int mdcfg0; 159 unsigned int mdcfg1; 160 unsigned int mdcfg2; 161 unsigned int mdmisc; 162 unsigned int mdref; 163 unsigned int mdrwd; 164 unsigned int mdor; 165 unsigned int mdasp; 166 unsigned int mpodtctrl; 167 unsigned int mpzqhwctrl; 168 unsigned int mprddlctl; 169 }; 170 171 void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr); 172 173 #endif /* FSL_MMDC_H */ 174