1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCUCFG_H 8 #define MCUCFG_H 9 10 #include <stdint.h> 11 12 #include <platform_def.h> 13 14 struct mt6795_mcucfg_regs { 15 uint32_t mp0_ca7l_cache_config; 16 struct { 17 uint32_t mem_delsel0; 18 uint32_t mem_delsel1; 19 } mp0_cpu[4]; 20 uint32_t mp0_cache_mem_delsel0; 21 uint32_t mp0_cache_mem_delsel1; 22 uint32_t mp0_axi_config; 23 uint32_t mp0_misc_config[2]; 24 struct { 25 uint32_t rv_addr_lw; 26 uint32_t rv_addr_hw; 27 } mp0_rv_addr[4]; 28 uint32_t mp0_ca7l_cfg_dis; 29 uint32_t mp0_ca7l_clken_ctrl; 30 uint32_t mp0_ca7l_rst_ctrl; 31 uint32_t mp0_ca7l_misc_config; 32 uint32_t mp0_ca7l_dbg_pwr_ctrl; 33 uint32_t mp0_rw_rsvd0; 34 uint32_t mp0_rw_rsvd1; 35 uint32_t mp0_ro_rsvd; 36 uint32_t reserved0_0[100]; 37 uint32_t mp1_cpucfg; 38 uint32_t mp1_miscdbg; 39 uint32_t reserved0_1[13]; 40 uint32_t mp1_rst_ctl; 41 uint32_t mp1_clkenm_div; 42 uint32_t reserved0_2[7]; 43 uint32_t mp1_config_res; 44 uint32_t reserved0_3[13]; 45 struct { 46 uint32_t rv_addr_lw; 47 uint32_t rv_addr_hw; 48 } mp1_rv_addr[2]; 49 uint32_t reserved0_4[84]; 50 uint32_t mp0_rst_status; /* 0x400 */ 51 uint32_t mp0_dbg_ctrl; 52 uint32_t mp0_dbg_flag; 53 uint32_t mp0_ca7l_ir_mon; 54 struct { 55 uint32_t pc_lw; 56 uint32_t pc_hw; 57 uint32_t fp_arch32; 58 uint32_t sp_arch32; 59 uint32_t fp_arch64_lw; 60 uint32_t fp_arch64_hw; 61 uint32_t sp_arch64_lw; 62 uint32_t sp_arch64_hw; 63 } mp0_dbg_core[4]; 64 uint32_t dfd_ctrl; 65 uint32_t dfd_cnt_l; 66 uint32_t dfd_cnt_h; 67 uint32_t misccfg_mp0_rw_rsvd; 68 uint32_t misccfg_sec_vio_status0; 69 uint32_t misccfg_sec_vio_status1; 70 uint32_t reserved1[22]; 71 uint32_t misccfg_rw_rsvd; /* 0x500 */ 72 uint32_t mcusys_dbg_mon_sel_a; 73 uint32_t mcusys_dbg_mon; 74 uint32_t reserved2[61]; 75 uint32_t mcusys_config_a; /* 0x600 */ 76 uint32_t mcusys_config1_a; 77 uint32_t mcusys_gic_peribase_a; 78 uint32_t reserved3; 79 uint32_t sec_range0_start; /* 0x610 */ 80 uint32_t sec_range0_end; 81 uint32_t sec_range_enable; 82 uint32_t reserved4; 83 uint32_t int_pol_ctl[8]; /* 0x620 */ 84 uint32_t aclken_div; /* 0x640 */ 85 uint32_t pclken_div; 86 uint32_t l2c_sram_ctrl; 87 uint32_t armpll_jit_ctrl; 88 uint32_t cci_addrmap; /* 0x650 */ 89 uint32_t cci_config; 90 uint32_t cci_periphbase; 91 uint32_t cci_nevntcntovfl; 92 uint32_t cci_clk_ctrl; /* 0x660 */ 93 uint32_t cci_acel_s1_ctrl; 94 uint32_t bus_fabric_dcm_ctrl; 95 uint32_t reserved5; 96 uint32_t xgpt_ctl; /* 0x670 */ 97 uint32_t xgpt_idx; 98 uint32_t ptpod2_ctl0; 99 uint32_t ptpod2_ctl1; 100 uint32_t mcusys_revid; 101 uint32_t mcusys_rw_rsvd0; 102 uint32_t mcusys_rw_rsvd1; 103 }; 104 105 static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE; 106 107 /* cpu boot mode */ 108 #define MP0_CPUCFG_64BIT_SHIFT 12 109 #define MP1_CPUCFG_64BIT_SHIFT 28 110 #define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) 111 #define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) 112 113 /* scu related */ 114 enum { 115 MP0_ACINACTM_SHIFT = 4, 116 MP1_ACINACTM_SHIFT = 0, 117 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, 118 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT 119 }; 120 121 enum { 122 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, 123 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, 124 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, 125 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, 126 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, 127 128 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 129 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 130 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 131 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 132 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 133 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 134 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 135 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 136 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 137 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 138 }; 139 140 enum { 141 MP1_AINACTS_SHIFT = 4, 142 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT 143 }; 144 145 enum { 146 MP1_SW_CG_GEN_SHIFT = 12, 147 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT 148 }; 149 150 enum { 151 MP1_L2RSTDISABLE_SHIFT = 14, 152 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT 153 }; 154 155 #endif /* MCUCFG_H */ 156