1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
14 #include "mt8195-reg.h"
15 #include "mt8195-audsys-clk.h"
16
17 static const char *aud_clks[MT8195_CLK_NUM] = {
18 /* xtal */
19 [MT8195_CLK_XTAL_26M] = "clk26m",
20 /* divider */
21 [MT8195_CLK_TOP_APLL1] = "apll1_ck",
22 [MT8195_CLK_TOP_APLL2] = "apll2_ck",
23 [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
24 [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
25 [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
26 [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
27 [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
28 /* mux */
29 [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
30 [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
31 [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
32 [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
33 [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
34 [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
35 [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
36 [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
37 [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
38 /* clock gate */
39 [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
40 [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
41 /* afe clock gate */
42 [MT8195_CLK_AUD_AFE] = "aud_afe",
43 [MT8195_CLK_AUD_APLL] = "aud_apll",
44 [MT8195_CLK_AUD_APLL2] = "aud_apll2",
45 [MT8195_CLK_AUD_DAC] = "aud_dac",
46 [MT8195_CLK_AUD_ADC] = "aud_adc",
47 [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
48 [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
49 [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
50 [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
51 [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
52 [MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
53 [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
54 [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
55 [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
56 [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
57 [MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
58 [MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
59 [MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
60 [MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
61 [MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
62 [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
63 [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
64 [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
65 [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
66 [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
67 [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
68 [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
69 [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
70 [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
71 [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
72 [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
73 [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
74 [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
75 [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
76 [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
77 [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
78 };
79
mt8195_afe_get_mclk_source_clk_id(int sel)80 int mt8195_afe_get_mclk_source_clk_id(int sel)
81 {
82 switch (sel) {
83 case MT8195_MCK_SEL_26M:
84 return MT8195_CLK_XTAL_26M;
85 case MT8195_MCK_SEL_APLL1:
86 return MT8195_CLK_TOP_APLL1;
87 case MT8195_MCK_SEL_APLL2:
88 return MT8195_CLK_TOP_APLL2;
89 default:
90 return -EINVAL;
91 }
92 }
93
mt8195_afe_get_mclk_source_rate(struct mtk_base_afe * afe,int apll)94 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
95 {
96 struct mt8195_afe_private *afe_priv = afe->platform_priv;
97 int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
98
99 if (clk_id < 0) {
100 dev_dbg(afe->dev, "invalid clk id\n");
101 return 0;
102 }
103
104 return clk_get_rate(afe_priv->clk[clk_id]);
105 }
106
mt8195_afe_get_default_mclk_source_by_rate(int rate)107 int mt8195_afe_get_default_mclk_source_by_rate(int rate)
108 {
109 return ((rate % 8000) == 0) ?
110 MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
111 }
112
mt8195_afe_init_clock(struct mtk_base_afe * afe)113 int mt8195_afe_init_clock(struct mtk_base_afe *afe)
114 {
115 struct mt8195_afe_private *afe_priv = afe->platform_priv;
116 int i;
117
118 mt8195_audsys_clk_register(afe);
119
120 afe_priv->clk =
121 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
122 GFP_KERNEL);
123 if (!afe_priv->clk)
124 return -ENOMEM;
125
126 for (i = 0; i < MT8195_CLK_NUM; i++) {
127 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
128 if (IS_ERR(afe_priv->clk[i])) {
129 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
130 __func__, aud_clks[i],
131 PTR_ERR(afe_priv->clk[i]));
132 return PTR_ERR(afe_priv->clk[i]);
133 }
134 }
135
136 return 0;
137 }
138
mt8195_afe_deinit_clock(struct mtk_base_afe * afe)139 void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
140 {
141 mt8195_audsys_clk_unregister(afe);
142 }
143
mt8195_afe_enable_clk(struct mtk_base_afe * afe,struct clk * clk)144 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
145 {
146 int ret;
147
148 if (clk) {
149 ret = clk_prepare_enable(clk);
150 if (ret) {
151 dev_dbg(afe->dev, "%s(), failed to enable clk\n",
152 __func__);
153 return ret;
154 }
155 } else {
156 dev_dbg(afe->dev, "NULL clk\n");
157 }
158 return 0;
159 }
160 EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
161
mt8195_afe_disable_clk(struct mtk_base_afe * afe,struct clk * clk)162 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
163 {
164 if (clk)
165 clk_disable_unprepare(clk);
166 else
167 dev_dbg(afe->dev, "NULL clk\n");
168 }
169 EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
170
mt8195_afe_prepare_clk(struct mtk_base_afe * afe,struct clk * clk)171 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
172 {
173 int ret;
174
175 if (clk) {
176 ret = clk_prepare(clk);
177 if (ret) {
178 dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
179 __func__);
180 return ret;
181 }
182 } else {
183 dev_dbg(afe->dev, "NULL clk\n");
184 }
185 return 0;
186 }
187
mt8195_afe_unprepare_clk(struct mtk_base_afe * afe,struct clk * clk)188 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
189 {
190 if (clk)
191 clk_unprepare(clk);
192 else
193 dev_dbg(afe->dev, "NULL clk\n");
194 }
195
mt8195_afe_enable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)196 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
197 {
198 int ret;
199
200 if (clk) {
201 ret = clk_enable(clk);
202 if (ret) {
203 dev_dbg(afe->dev, "%s(), failed to clk enable\n",
204 __func__);
205 return ret;
206 }
207 } else {
208 dev_dbg(afe->dev, "NULL clk\n");
209 }
210 return 0;
211 }
212
mt8195_afe_disable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)213 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
214 {
215 if (clk)
216 clk_disable(clk);
217 else
218 dev_dbg(afe->dev, "NULL clk\n");
219 }
220
mt8195_afe_set_clk_rate(struct mtk_base_afe * afe,struct clk * clk,unsigned int rate)221 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
222 unsigned int rate)
223 {
224 int ret;
225
226 if (clk) {
227 ret = clk_set_rate(clk, rate);
228 if (ret) {
229 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
230 __func__);
231 return ret;
232 }
233 }
234
235 return 0;
236 }
237
mt8195_afe_set_clk_parent(struct mtk_base_afe * afe,struct clk * clk,struct clk * parent)238 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
239 struct clk *parent)
240 {
241 int ret;
242
243 if (clk && parent) {
244 ret = clk_set_parent(clk, parent);
245 if (ret) {
246 dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
247 __func__);
248 return ret;
249 }
250 }
251
252 return 0;
253 }
254
get_top_cg_reg(unsigned int cg_type)255 static unsigned int get_top_cg_reg(unsigned int cg_type)
256 {
257 switch (cg_type) {
258 case MT8195_TOP_CG_A1SYS_TIMING:
259 case MT8195_TOP_CG_A2SYS_TIMING:
260 case MT8195_TOP_CG_26M_TIMING:
261 return ASYS_TOP_CON;
262 default:
263 return 0;
264 }
265 }
266
get_top_cg_mask(unsigned int cg_type)267 static unsigned int get_top_cg_mask(unsigned int cg_type)
268 {
269 switch (cg_type) {
270 case MT8195_TOP_CG_A1SYS_TIMING:
271 return ASYS_TOP_CON_A1SYS_TIMING_ON;
272 case MT8195_TOP_CG_A2SYS_TIMING:
273 return ASYS_TOP_CON_A2SYS_TIMING_ON;
274 case MT8195_TOP_CG_26M_TIMING:
275 return ASYS_TOP_CON_26M_TIMING_ON;
276 default:
277 return 0;
278 }
279 }
280
get_top_cg_on_val(unsigned int cg_type)281 static unsigned int get_top_cg_on_val(unsigned int cg_type)
282 {
283 switch (cg_type) {
284 case MT8195_TOP_CG_A1SYS_TIMING:
285 case MT8195_TOP_CG_A2SYS_TIMING:
286 case MT8195_TOP_CG_26M_TIMING:
287 return get_top_cg_mask(cg_type);
288 default:
289 return 0;
290 }
291 }
292
get_top_cg_off_val(unsigned int cg_type)293 static unsigned int get_top_cg_off_val(unsigned int cg_type)
294 {
295 switch (cg_type) {
296 case MT8195_TOP_CG_A1SYS_TIMING:
297 case MT8195_TOP_CG_A2SYS_TIMING:
298 case MT8195_TOP_CG_26M_TIMING:
299 return 0;
300 default:
301 return get_top_cg_mask(cg_type);
302 }
303 }
304
mt8195_afe_enable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)305 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
306 {
307 unsigned int reg = get_top_cg_reg(cg_type);
308 unsigned int mask = get_top_cg_mask(cg_type);
309 unsigned int val = get_top_cg_on_val(cg_type);
310
311 regmap_update_bits(afe->regmap, reg, mask, val);
312 return 0;
313 }
314
mt8195_afe_disable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)315 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
316 {
317 unsigned int reg = get_top_cg_reg(cg_type);
318 unsigned int mask = get_top_cg_mask(cg_type);
319 unsigned int val = get_top_cg_off_val(cg_type);
320
321 regmap_update_bits(afe->regmap, reg, mask, val);
322 return 0;
323 }
324
mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe * afe)325 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
326 {
327 struct mt8195_afe_private *afe_priv = afe->platform_priv;
328 int i;
329 unsigned int clk_array[] = {
330 MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
331 MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
332 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
333 MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
334 MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
335 MT8195_CLK_AUD_AFE, /* AFE HW master switch */
336 MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
337 MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
338 };
339
340 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
341 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
342
343 return 0;
344 }
345
mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe * afe)346 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
347 {
348 struct mt8195_afe_private *afe_priv = afe->platform_priv;
349 int i;
350 unsigned int clk_array[] = {
351 MT8195_CLK_AUD_A1SYS,
352 MT8195_CLK_AUD_A1SYS_HP,
353 MT8195_CLK_AUD_AFE,
354 MT8195_CLK_INFRA_AO_AUDIO_26M_B,
355 MT8195_CLK_TOP_AUD_INTBUS_SEL,
356 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
357 MT8195_CLK_TOP_AUDIO_H_SEL,
358 MT8195_CLK_SCP_ADSP_AUDIODSP,
359 };
360
361 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
362 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
363
364 return 0;
365 }
366
mt8195_afe_enable_afe_on(struct mtk_base_afe * afe)367 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
368 {
369 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
370 return 0;
371 }
372
mt8195_afe_disable_afe_on(struct mtk_base_afe * afe)373 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
374 {
375 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
376 return 0;
377 }
378
mt8195_afe_enable_timing_sys(struct mtk_base_afe * afe)379 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
380 {
381 struct mt8195_afe_private *afe_priv = afe->platform_priv;
382 int i;
383 unsigned int clk_array[] = {
384 MT8195_CLK_AUD_A1SYS,
385 MT8195_CLK_AUD_A2SYS,
386 };
387 unsigned int cg_array[] = {
388 MT8195_TOP_CG_A1SYS_TIMING,
389 MT8195_TOP_CG_A2SYS_TIMING,
390 MT8195_TOP_CG_26M_TIMING,
391 };
392
393 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
394 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
395
396 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
397 mt8195_afe_enable_top_cg(afe, cg_array[i]);
398
399 return 0;
400 }
401
mt8195_afe_disable_timing_sys(struct mtk_base_afe * afe)402 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
403 {
404 struct mt8195_afe_private *afe_priv = afe->platform_priv;
405 int i;
406 unsigned int clk_array[] = {
407 MT8195_CLK_AUD_A2SYS,
408 MT8195_CLK_AUD_A1SYS,
409 };
410 unsigned int cg_array[] = {
411 MT8195_TOP_CG_26M_TIMING,
412 MT8195_TOP_CG_A2SYS_TIMING,
413 MT8195_TOP_CG_A1SYS_TIMING,
414 };
415
416 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
417 mt8195_afe_disable_top_cg(afe, cg_array[i]);
418
419 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
420 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
421
422 return 0;
423 }
424
mt8195_afe_enable_main_clock(struct mtk_base_afe * afe)425 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
426 {
427 mt8195_afe_enable_timing_sys(afe);
428
429 mt8195_afe_enable_afe_on(afe);
430
431 return 0;
432 }
433
mt8195_afe_disable_main_clock(struct mtk_base_afe * afe)434 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
435 {
436 mt8195_afe_disable_afe_on(afe);
437
438 mt8195_afe_disable_timing_sys(afe);
439
440 return 0;
441 }
442