1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018 MediaTek Inc.
4  * Author: Jie Qiu <jie.qiu@mediatek.com>
5  */
6 
7 #include "phy-mtk-hdmi.h"
8 
9 static int mtk_hdmi_phy_power_on(struct phy *phy);
10 static int mtk_hdmi_phy_power_off(struct phy *phy);
11 
12 static const struct phy_ops mtk_hdmi_phy_dev_ops = {
13 	.power_on = mtk_hdmi_phy_power_on,
14 	.power_off = mtk_hdmi_phy_power_off,
15 	.owner = THIS_MODULE,
16 };
17 
mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy * hdmi_phy,u32 offset,u32 bits)18 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
19 			     u32 bits)
20 {
21 	void __iomem *reg = hdmi_phy->regs + offset;
22 	u32 tmp;
23 
24 	tmp = readl(reg);
25 	tmp &= ~bits;
26 	writel(tmp, reg);
27 }
28 
mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy * hdmi_phy,u32 offset,u32 bits)29 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
30 			   u32 bits)
31 {
32 	void __iomem *reg = hdmi_phy->regs + offset;
33 	u32 tmp;
34 
35 	tmp = readl(reg);
36 	tmp |= bits;
37 	writel(tmp, reg);
38 }
39 
mtk_hdmi_phy_mask(struct mtk_hdmi_phy * hdmi_phy,u32 offset,u32 val,u32 mask)40 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
41 		       u32 val, u32 mask)
42 {
43 	void __iomem *reg = hdmi_phy->regs + offset;
44 	u32 tmp;
45 
46 	tmp = readl(reg);
47 	tmp = (tmp & ~mask) | (val & mask);
48 	writel(tmp, reg);
49 }
50 
to_mtk_hdmi_phy(struct clk_hw * hw)51 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
52 {
53 	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
54 }
55 
mtk_hdmi_phy_power_on(struct phy * phy)56 static int mtk_hdmi_phy_power_on(struct phy *phy)
57 {
58 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
59 	int ret;
60 
61 	ret = clk_prepare_enable(hdmi_phy->pll);
62 	if (ret < 0)
63 		return ret;
64 
65 	hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
66 	return 0;
67 }
68 
mtk_hdmi_phy_power_off(struct phy * phy)69 static int mtk_hdmi_phy_power_off(struct phy *phy)
70 {
71 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
72 
73 	hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
74 	clk_disable_unprepare(hdmi_phy->pll);
75 
76 	return 0;
77 }
78 
79 static const struct phy_ops *
mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy * hdmi_phy)80 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
81 {
82 	if (hdmi_phy && hdmi_phy->conf &&
83 	    hdmi_phy->conf->hdmi_phy_enable_tmds &&
84 	    hdmi_phy->conf->hdmi_phy_disable_tmds)
85 		return &mtk_hdmi_phy_dev_ops;
86 
87 	if (hdmi_phy)
88 		dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
89 	return NULL;
90 }
91 
mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy * hdmi_phy,struct clk_init_data * clk_init)92 static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
93 				      struct clk_init_data *clk_init)
94 {
95 	clk_init->flags = hdmi_phy->conf->flags;
96 	clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
97 }
98 
mtk_hdmi_phy_probe(struct platform_device * pdev)99 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
100 {
101 	struct device *dev = &pdev->dev;
102 	struct mtk_hdmi_phy *hdmi_phy;
103 	struct clk *ref_clk;
104 	const char *ref_clk_name;
105 	struct clk_init_data clk_init = {
106 		.num_parents = 1,
107 		.parent_names = (const char * const *)&ref_clk_name,
108 	};
109 
110 	struct phy *phy;
111 	struct phy_provider *phy_provider;
112 	int ret;
113 
114 	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
115 	if (!hdmi_phy)
116 		return -ENOMEM;
117 
118 	hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
119 	if (IS_ERR(hdmi_phy->regs))
120 		return PTR_ERR(hdmi_phy->regs);
121 
122 	ref_clk = devm_clk_get(dev, "pll_ref");
123 	if (IS_ERR(ref_clk)) {
124 		ret = PTR_ERR(ref_clk);
125 		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
126 			ret);
127 		return ret;
128 	}
129 	ref_clk_name = __clk_get_name(ref_clk);
130 
131 	ret = of_property_read_string(dev->of_node, "clock-output-names",
132 				      &clk_init.name);
133 	if (ret < 0) {
134 		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
135 		return ret;
136 	}
137 
138 	hdmi_phy->dev = dev;
139 	hdmi_phy->conf =
140 		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
141 	mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
142 	hdmi_phy->pll_hw.init = &clk_init;
143 	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
144 	if (IS_ERR(hdmi_phy->pll)) {
145 		ret = PTR_ERR(hdmi_phy->pll);
146 		dev_err(dev, "Failed to register PLL: %d\n", ret);
147 		return ret;
148 	}
149 
150 	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
151 				   &hdmi_phy->ibias);
152 	if (ret < 0) {
153 		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
154 		return ret;
155 	}
156 
157 	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
158 				   &hdmi_phy->ibias_up);
159 	if (ret < 0) {
160 		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
161 		return ret;
162 	}
163 
164 	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
165 	hdmi_phy->drv_imp_clk = 0x30;
166 	hdmi_phy->drv_imp_d2 = 0x30;
167 	hdmi_phy->drv_imp_d1 = 0x30;
168 	hdmi_phy->drv_imp_d0 = 0x30;
169 
170 	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
171 	if (IS_ERR(phy)) {
172 		dev_err(dev, "Failed to create HDMI PHY\n");
173 		return PTR_ERR(phy);
174 	}
175 	phy_set_drvdata(phy, hdmi_phy);
176 
177 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
178 	if (IS_ERR(phy_provider)) {
179 		dev_err(dev, "Failed to register HDMI PHY\n");
180 		return PTR_ERR(phy_provider);
181 	}
182 
183 	if (hdmi_phy->conf->pll_default_off)
184 		hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
185 
186 	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
187 				   hdmi_phy->pll);
188 }
189 
190 static const struct of_device_id mtk_hdmi_phy_match[] = {
191 	{ .compatible = "mediatek,mt2701-hdmi-phy",
192 	  .data = &mtk_hdmi_phy_2701_conf,
193 	},
194 	{ .compatible = "mediatek,mt8173-hdmi-phy",
195 	  .data = &mtk_hdmi_phy_8173_conf,
196 	},
197 	{},
198 };
199 MODULE_DEVICE_TABLE(of, mtk_hdmi_phy_match);
200 
201 static struct platform_driver mtk_hdmi_phy_driver = {
202 	.probe = mtk_hdmi_phy_probe,
203 	.driver = {
204 		.name = "mediatek-hdmi-phy",
205 		.of_match_table = mtk_hdmi_phy_match,
206 	},
207 };
208 module_platform_driver(mtk_hdmi_phy_driver);
209 
210 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
211 MODULE_LICENSE("GPL v2");
212