Searched defs:mul (Results 1 – 10 of 10) sorted by relevance
| /u-boot/arch/arm/mach-at91/arm920t/ |
| A D | clock.c | 44 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
93 unsigned mul, div; in at91_pll_rate() local
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| /u-boot/include/linux/ |
| A D | math64.h | 150 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr()
157 static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift) in mul_u64_u64_shr()
166 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr()
229 static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) in mul_u64_u32_div()
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| /u-boot/arch/arm/mach-at91/arm926ejs/ |
| A D | clock.c | 44 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
101 unsigned mul, div; in at91_pll_rate() local
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| /u-boot/drivers/clk/ |
| A D | clk_boston.c | 32 uint32_t in_rate, mul, div; in clk_boston_get_rate() local
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| A D | clk_pic32.c | 286 u32 v, idiv, mul; in pic32_get_mpll_rate() local
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| A D | clk_zynq.c | 136 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
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| A D | clk_zynqmp.c | 349 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
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| /u-boot/arch/arm/mach-at91/armv7/ |
| A D | clock.c | 43 unsigned mul, div; in at91_pll_rate() local
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| /u-boot/drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 59 static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate, in sam9x60_frac_pll_compute_mul_frac()
145 u32 mul, frac, val; in sam9x60_frac_pll_get_rate() local
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| /u-boot/drivers/clk/aspeed/ |
| A D | clk_ast2600.c | 145 uint32_t mul = 1, div = 1; in ast2600_get_pll_rate() local
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