1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell SD Host Controller Interface
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <malloc.h>
9 #include <sdhci.h>
10 #include <asm/global_data.h>
11 #include <linux/mbus.h>
12
13 #define MVSDH_NAME "mv_sdh"
14
15 #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
16 #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
17
sdhci_mvebu_mbus_config(void __iomem * base)18 static void sdhci_mvebu_mbus_config(void __iomem *base)
19 {
20 const struct mbus_dram_target_info *dram;
21 int i;
22
23 dram = mvebu_mbus_dram_info();
24
25 for (i = 0; i < 4; i++) {
26 writel(0, base + SDHCI_WINDOW_CTRL(i));
27 writel(0, base + SDHCI_WINDOW_BASE(i));
28 }
29
30 for (i = 0; i < dram->num_cs; i++) {
31 const struct mbus_dram_window *cs = dram->cs + i;
32
33 /* Write size, attributes and target id to control register */
34 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
35 (dram->mbus_dram_target_id << 4) | 1,
36 base + SDHCI_WINDOW_CTRL(i));
37
38 /* Write base address to base register */
39 writel(cs->base, base + SDHCI_WINDOW_BASE(i));
40 }
41 }
42
43 #ifndef CONFIG_DM_MMC
44
45 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
46 static struct sdhci_ops mv_ops;
47
48 #if defined(CONFIG_SHEEVA_88SV331xV5)
49 #define SD_CE_ATA_2 0xEA
50 #define MMC_CARD 0x1000
51 #define MMC_WIDTH 0x0100
mv_sdhci_writeb(struct sdhci_host * host,u8 val,int reg)52 static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
53 {
54 struct mmc *mmc = host->mmc;
55 u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
56
57 if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
58 if (mmc->bus_width == 8)
59 writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
60 else
61 writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
62 }
63
64 writeb(val, host->ioaddr + reg);
65 }
66
67 #else
68 #define mv_sdhci_writeb NULL
69 #endif /* CONFIG_SHEEVA_88SV331xV5 */
70 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
71
mv_sdh_init(unsigned long regbase,u32 max_clk,u32 min_clk,u32 quirks)72 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
73 {
74 struct sdhci_host *host = NULL;
75 host = calloc(1, sizeof(*host));
76 if (!host) {
77 printf("sdh_host malloc fail!\n");
78 return -ENOMEM;
79 }
80
81 host->name = MVSDH_NAME;
82 host->ioaddr = (void *)regbase;
83 host->quirks = quirks;
84 host->max_clk = max_clk;
85 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
86 memset(&mv_ops, 0, sizeof(struct sdhci_ops));
87 mv_ops.write_b = mv_sdhci_writeb;
88 host->ops = &mv_ops;
89 #endif
90
91 if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
92 /* Configure SDHCI MBUS mbus bridge windows */
93 sdhci_mvebu_mbus_config((void __iomem *)regbase);
94 }
95
96 return add_sdhci(host, 0, min_clk);
97 }
98
99 #else
100
101 DECLARE_GLOBAL_DATA_PTR;
102
103 struct mv_sdhci_plat {
104 struct mmc_config cfg;
105 struct mmc mmc;
106 };
107
mv_sdhci_probe(struct udevice * dev)108 static int mv_sdhci_probe(struct udevice *dev)
109 {
110 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
111 struct mv_sdhci_plat *plat = dev_get_plat(dev);
112 struct sdhci_host *host = dev_get_priv(dev);
113 int ret;
114
115 host->name = MVSDH_NAME;
116 host->ioaddr = dev_read_addr_ptr(dev);
117 host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
118 host->mmc = &plat->mmc;
119 host->mmc->dev = dev;
120 host->mmc->priv = host;
121
122 ret = mmc_of_parse(dev, &plat->cfg);
123 if (ret)
124 return ret;
125
126 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
127 if (ret)
128 return ret;
129
130 if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
131 /* Configure SDHCI MBUS mbus bridge windows */
132 sdhci_mvebu_mbus_config(host->ioaddr);
133 }
134
135 upriv->mmc = host->mmc;
136
137 return sdhci_probe(dev);
138 }
139
mv_sdhci_bind(struct udevice * dev)140 static int mv_sdhci_bind(struct udevice *dev)
141 {
142 struct mv_sdhci_plat *plat = dev_get_plat(dev);
143
144 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
145 }
146
147 static const struct udevice_id mv_sdhci_ids[] = {
148 { .compatible = "marvell,armada-380-sdhci" },
149 { }
150 };
151
152 U_BOOT_DRIVER(mv_sdhci_drv) = {
153 .name = MVSDH_NAME,
154 .id = UCLASS_MMC,
155 .of_match = mv_sdhci_ids,
156 .bind = mv_sdhci_bind,
157 .probe = mv_sdhci_probe,
158 .ops = &sdhci_ops,
159 .priv_auto = sizeof(struct sdhci_host),
160 .plat_auto = sizeof(struct mv_sdhci_plat),
161 };
162 #endif /* CONFIG_DM_MMC */
163