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/trusted-firmware-a/docs/build/TF-A_2.5/_static/
A Dunderscore.js6 var n="1.13.1",r="object"==typeof self&&self.self===self&&self||"object"==typeof global&&global.glo… argument
A Djquery.js2 …nction(e,t){"use strict";"object"==typeof module&&"object"==typeof module.exports?module.exports=e… argument
/trusted-firmware-a/plat/rockchip/rk3399/include/shared/
A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) argument
81 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) argument
82 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
93 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) argument
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A Dmisc_regs.h21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) argument
22 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) argument
/trusted-firmware-a/plat/rockchip/rk3399/drivers/secure/
A Dsecure.h13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) argument
14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) argument
15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) argument
16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ argument
20 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) argument
21 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) argument
22 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) argument
23 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) argument
55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) argument
60 #define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) argument
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/trusted-firmware-a/fdts/
A Dfvp-defs-dynamiq.dtsi30 #define CPU(n, r) \ argument
41 #define THREAD(n) \ argument
46 #define CORE(n) \ argument
53 #define CORE(n) \ argument
68 #define CLUSTER(n) \ argument
85 #define CLUSTER(n) \ argument
106 #define CLUSTER(n) \ argument
131 #define CLUSTER(n) \ argument
160 #define CLUSTER(n) \ argument
193 #define CLUSTER(n) \ argument
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A Dfvp-defs.dtsi34 #define CLS(n) (n / CPUS_PER_CLUSTER) argument
37 #define POS(n) (n % CPUS_PER_CLUSTER) argument
39 #define ADR(n, c, p) \ argument
79 #define CPU(n, c, p) \ argument
332 #define CORE(n) \ argument
339 #define CLUSTER(n) \ argument
344 #define CLUSTER(n) \ argument
351 #define CLUSTER(n) \ argument
359 #define CLUSTER(n) \ argument
/trusted-firmware-a/docs/build/TF-A_2.5/_static/js/
A Dtheme.js1 !function(n){var e={};function t(i){if(e[i])return e[i].exports;var o=e[i]={i:i,l:!1,exports:{}};re… argument
A Dbadge_only.js1 !function(e){var t={};function r(n){if(t[n])return t[n].exports;var o=t[n]={i:n,l:!1,exports:{}};re… argument
/trusted-firmware-a/include/drivers/rpi3/gpio/
A Drpi3_gpio.h18 #define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04)) argument
19 #define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C)) argument
20 #define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28)) argument
21 #define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34)) argument
23 #define RPI3_GPIO_GPPUDCLK(n) (((n) * U(0x04)) + U(0x98)) argument
/trusted-firmware-a/drivers/arm/gic/common/
A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
113 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
124 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
138 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr() local
171 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr() local
226 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr() local
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/trusted-firmware-a/drivers/arm/gic/v2/
A Dgicdv2_helpers.c23 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
34 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
45 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
56 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
67 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
111 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
122 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
136 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr() local
169 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr() local
224 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr() local
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A Dgicv2_helpers.c24 unsigned n = id >> ITARGETSR_SHIFT; in gicd_read_itargetsr() local
34 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_read_cpendsgir() local
44 unsigned n = id >> SPENDSGIR_SHIFT; in gicd_read_spendsgir() local
54 unsigned n = id >> ITARGETSR_SHIFT; in gicd_write_itargetsr() local
64 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_write_cpendsgir() local
74 unsigned n = id >> SPENDSGIR_SHIFT; in gicd_write_spendsgir() local
/trusted-firmware-a/plat/rockchip/rk3328/drivers/soc/
A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) argument
67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) argument
73 #define GRF_SOC_CON(n) (0x400 + (n) * 4) argument
74 #define GRF_SOC_STATUS(n) (0x480 + (n) * 4) argument
75 #define GRF_CPU_STATUS(n) (0x520 + (n) * 4) argument
76 #define GRF_OS_REG(n) (0x5c8 + (n) * 4) argument
77 #define DDRGRF_SOC_CON(n) (0x000 + (n) * 4) argument
78 #define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
79 #define SGRF_SOC_CON(n) (0x000 + (n) * 4) argument
80 #define SGRF_DMAC_CON(n) (0x100 + (n) * 4) argument
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/trusted-firmware-a/include/plat/arm/css/common/
A Dcss_pm.h51 #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ argument
53 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
54 #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ argument
56 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
/trusted-firmware-a/drivers/allwinner/
A Dsunxi_msgbox.c22 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
23 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
25 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
28 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
31 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
/trusted-firmware-a/plat/rockchip/rk3399/drivers/soc/
A Dsoc.h15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
32 #define REFDIV(n) ((0x3F << 16) | n) argument
33 #define PLL_LOCK(n) ((n >> 31) & 0x1) argument
46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) argument
56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) argument
57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) argument
147 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) argument
190 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) argument
225 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) argument
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/trusted-firmware-a/drivers/arm/gic/v3/
A Dgic600ae_fmu_helpers.c31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \ argument
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr()
126 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n) in gic_fmu_read_errstatus()
203 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val) in gic_fmu_write_errctlr()
212 void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val) in gic_fmu_write_errstatus()
/trusted-firmware-a/plat/rockchip/rk3399/drivers/dram/
A Dsuspend.c29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
32 #define FBDIV_ENC(n) ((n) << 16) argument
33 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) argument
34 #define POSTDIV2_ENC(n) ((n) << 12) argument
35 #define POSTDIV2_DEC(n) (((n) >> 12) & 0x7) argument
36 #define POSTDIV1_ENC(n) ((n) << 8) argument
37 #define POSTDIV1_DEC(n) (((n) >> 8) & 0x7) argument
38 #define REFDIV_ENC(n) (n) argument
39 #define REFDIV_DEC(n) ((n) & 0x3f) argument
45 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7)) argument
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/trusted-firmware-a/plat/allwinner/sun50i_r329/include/
A Dsunxi_cpucfg.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
/trusted-firmware-a/plat/rockchip/rk3288/drivers/secure/
A Dsecure.h15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) argument
30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) argument
31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) argument
32 #define SGRF_CPU_CON(n) (0x40 + (n) * 4) argument
33 #define SGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
/trusted-firmware-a/plat/allwinner/sun50i_h6/include/
A Dsunxi_cpucfg.h19 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
20 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
/trusted-firmware-a/plat/allwinner/sun50i_h616/include/
A Dsunxi_cpucfg.h19 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
20 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
/trusted-firmware-a/lib/libc/
A Dsnprintf.c22 static void string_print(char **s, size_t n, size_t *chars_printed, in string_print()
31 static void unsigned_num_print(char **s, size_t n, size_t *chars_printed, in unsigned_num_print()
104 int vsnprintf(char *s, size_t n, const char *fmt, va_list args) in vsnprintf()
249 int snprintf(char *s, size_t n, const char *fmt, ...) in snprintf()
/trusted-firmware-a/plat/allwinner/sun50i_a64/include/
A Dsunxi_cpucfg.h22 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8) argument
23 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \ argument

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