1 /*
2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <denver.h>
14 #include <lib/mmio.h>
15
16 #include <mce_private.h>
17 #include <platform_def.h>
18 #include <t194_nvg.h>
19 #include <tegra_private.h>
20
21 #define ID_AFR0_EL1_CACHE_OPS_SHIFT U(12)
22 #define ID_AFR0_EL1_CACHE_OPS_MASK U(0xF)
23 /*
24 * Reports the major and minor version of this interface.
25 *
26 * NVGDATA[0:31]: SW(R) Minor Version
27 * NVGDATA[32:63]: SW(R) Major Version
28 */
nvg_get_version(void)29 uint64_t nvg_get_version(void)
30 {
31 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION);
32
33 return (uint64_t)nvg_get_result();
34 }
35
36 /*
37 * Set the expected wake time in TSC ticks for the next low-power state the
38 * core enters.
39 *
40 * NVGDATA[0:31]: SW(RW), WAKE_TIME
41 */
nvg_set_wake_time(uint32_t wake_time)42 void nvg_set_wake_time(uint32_t wake_time)
43 {
44 /* time (TSC ticks) until the core is expected to get a wake event */
45 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
46 }
47
48 /*
49 * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and
50 * SYSTEM_CSTATE values.
51 *
52 * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE
53 * NVGDATA[7]: SW(W), update cluster flag
54 * NVGDATA[8:10]: SW(RW), CG_CSTATE
55 * NVGDATA[15]: SW(W), update ccplex flag
56 * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE
57 * NVGDATA[23]: SW(W), update system flag
58 * NVGDATA[31]: SW(W), update wake mask flag
59 * NVGDATA[32:63]: SW(RW), WAKE_MASK
60 */
nvg_update_cstate_info(uint32_t cluster,uint32_t ccplex,uint32_t system,uint32_t wake_mask,uint8_t update_wake_mask)61 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
62 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask)
63 {
64 uint64_t val = 0;
65
66 /* update CLUSTER_CSTATE? */
67 if (cluster != 0U) {
68 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) |
69 CLUSTER_CSTATE_UPDATE_BIT;
70 }
71
72 /* update CCPLEX_CSTATE? */
73 if (ccplex != 0U) {
74 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
75 CCPLEX_CSTATE_UPDATE_BIT;
76 }
77
78 /* update SYSTEM_CSTATE? */
79 if (system != 0U) {
80 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
81 SYSTEM_CSTATE_UPDATE_BIT;
82 }
83
84 /* update wake mask value? */
85 if (update_wake_mask != 0U) {
86 val |= CSTATE_WAKE_MASK_UPDATE_BIT;
87 }
88
89 /* set the wake mask */
90 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT;
91
92 /* set the updated cstate info */
93 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
94 }
95
96 /*
97 * Return a non-zero value if the CCPLEX is able to enter SC7
98 *
99 * NVGDATA[0]: SW(R), Is allowed result
100 */
nvg_is_sc7_allowed(void)101 int32_t nvg_is_sc7_allowed(void)
102 {
103 /* issue command to check if SC7 is allowed */
104 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
105
106 /* 1 = SC7 allowed, 0 = SC7 not allowed */
107 return (int32_t)nvg_get_result();
108 }
109
110 /*
111 * Wake an offlined logical core. Note that a core is offlined by entering
112 * a C-state where the WAKE_MASK is all 0.
113 *
114 * NVGDATA[0:3]: SW(W) logical core to online
115 */
nvg_online_core(uint32_t core)116 int32_t nvg_online_core(uint32_t core)
117 {
118 int32_t ret = 0;
119
120 /* sanity check the core ID value */
121 if (core > (uint32_t)PLATFORM_CORE_COUNT) {
122 ERROR("%s: unknown core id (%d)\n", __func__, core);
123 ret = -EINVAL;
124 } else {
125 /* get a core online */
126 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
127 (uint64_t)core & MCE_CORE_ID_MASK);
128 }
129
130 return ret;
131 }
132
133 /*
134 * MC GSC (General Security Carveout) register values are expected to be
135 * changed by TrustZone ARM code after boot.
136 *
137 * NVGDATA[0:15] SW(R) GSC enun
138 */
nvg_update_ccplex_gsc(uint32_t gsc_idx)139 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
140 {
141 int32_t ret = 0;
142
143 /* sanity check GSC ID */
144 if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
145 ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
146 ret = -EINVAL;
147 } else {
148 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
149 (uint64_t)gsc_idx);
150 }
151
152 return ret;
153 }
154
155 /*
156 * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
157 */
nvg_roc_clean_cache_trbits(void)158 int32_t nvg_roc_clean_cache_trbits(void)
159 {
160 int32_t ret = 0;
161
162 /* check if cache flush through mts is supported */
163 if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
164 ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
165 if (nvg_cache_inval_all() == 0U) {
166 ERROR("%s: failed\n", __func__);
167 ret = -ENODEV;
168 }
169 } else {
170 ret = -ENOTSUP;
171 }
172
173 return ret;
174 }
175
176 /*
177 * Set the power state for a core
178 */
nvg_enter_cstate(uint32_t state,uint32_t wake_time)179 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
180 {
181 int32_t ret = 0;
182 uint64_t val = 0ULL;
183
184 /* check for allowed power state */
185 if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
186 (state != (uint32_t)TEGRA_NVG_CORE_C1) &&
187 (state != (uint32_t)TEGRA_NVG_CORE_C6) &&
188 (state != (uint32_t)TEGRA_NVG_CORE_C7))
189 {
190 ERROR("%s: unknown cstate (%u)\n", __func__, state);
191 ret = -EINVAL;
192 } else {
193 /* time (TSC ticks) until the core is expected to get a wake event */
194 nvg_set_wake_time(wake_time);
195
196 /* set the core cstate */
197 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
198 write_actlr_el1(val | (uint64_t)state);
199 }
200
201 return ret;
202 }
203
204 #if ENABLE_STRICT_CHECKING_MODE
205 /*
206 * Enable strict checking mode
207 *
208 * NVGDATA[3] strict_check ON + lock
209 */
nvg_enable_strict_checking_mode(void)210 void nvg_enable_strict_checking_mode(void)
211 {
212 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
213 STRICT_CHECKING_LOCKED_SET);
214
215 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
216 }
217
nvg_verify_strict_checking_mode(void)218 void nvg_verify_strict_checking_mode(void)
219 {
220 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
221 STRICT_CHECKING_LOCKED_SET);
222
223 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG);
224 assert(params == (uint64_t)nvg_get_result());
225 }
226 #endif
227
228 /*
229 * Request a reboot
230 *
231 * NVGDATA[0]: reboot command
232 */
nvg_system_reboot(void)233 void nvg_system_reboot(void)
234 {
235 /* issue command for reboot */
236 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
237 (uint64_t)TEGRA_NVG_REBOOT);
238 }
239
240 /*
241 * Request a shutdown
242 *
243 * NVGDATA[0]: shutdown command
244 */
nvg_system_shutdown(void)245 void nvg_system_shutdown(void)
246 {
247 /* issue command for shutdown */
248 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
249 (uint64_t)TEGRA_NVG_SHUTDOWN);
250 }
251
252 /*
253 * Request to clear CCPLEX->HSM correctable error signal.
254 * NVGDATA[1]: A write of 1 clears the CCPLEX->HSM correctable error signal,
255 * A write of 0 has no effect.
256 */
nvg_clear_hsm_corr_status(void)257 void nvg_clear_hsm_corr_status(void)
258 {
259 nvg_hsm_error_ctrl_channel_t status = { .bits = { .corr = 1U, }, };
260
261 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL, status.flat);
262 }
263