1 /* SPDX-License-Identifier: GPL-2.0+
2  *
3  * Copyright (C) 2016  Nexell Co., Ltd.
4  *
5  * Author: junghyun, kim <jhkim@nexell.co.kr>
6  */
7 
8 #ifndef _S5PXX18_SOC_MIPI_H_
9 #define _S5PXX18_SOC_MIPI_H_
10 
11 #define NUMBER_OF_MIPI_MODULE 1
12 #define PHY_BASEADDR_MIPI_MODULE	0xC00D0000
13 #define	PHY_BASEADDR_MIPI_LIST	\
14 		{ PHY_BASEADDR_MIPI_MODULE }
15 
16 #define nx_mipi_numberof_csi_channels 2
17 
18 struct nx_mipi_register_set {
19 	u32 csis_control;
20 	u32 csis_dphyctrl;
21 	u32 csis_config_ch0;
22 	u32 csis_dphysts;
23 	u32 csis_intmsk;
24 	u32 csis_intsrc;
25 	u32 csis_ctrl2;
26 	u32 csis_version;
27 	u32 csis_dphyctrl_0;
28 	u32 csis_dphyctrl_1;
29 	u32 __reserved0;
30 	u32 csis_resol_ch0;
31 	u32 __reserved1;
32 	u32 __reserved2;
33 	u32 sdw_config_ch0;
34 	u32 sdw_resol_ch0;
35 	u32 csis_config_ch1;
36 	u32 csis_resol_ch1;
37 	u32 sdw_config_ch1;
38 	u32 sdw_resol_ch1;
39 	u32 csis_config_ch2;
40 	u32 csis_resol_ch2;
41 	u32 sdw_config_ch2;
42 	u32 sdw_resol_ch2;
43 	u32 csis_config_ch3;
44 	u32 csis_resol_ch3;
45 	u32 sdw_config_ch3;
46 	u32 sdw_resol_3;
47 	u32 __reserved3[(16 + 128) / 4];
48 
49 	u32 dsim_status;
50 	u32 dsim_swrst;
51 	u32 dsim_clkctrl;
52 	u32 dsim_timeout;
53 	u32 dsim_config;
54 	u32 dsim_escmode;
55 	u32 dsim_mdresol;
56 	u32 dsim_mvporch;
57 	u32 dsim_mhporch;
58 	u32 dsim_msync;
59 	u32 dsim_sdresol;
60 	u32 dsim_intsrc;
61 	u32 dsim_intmsk;
62 	u32 dsim_pkthdr;
63 	u32 dsim_payload;
64 	u32 dsim_rxfifo;
65 	u32 dsim_fifothld;
66 	u32 dsim_fifoctrl;
67 	u32 dsim_memacchr;
68 	u32 dsim_pllctrl;
69 	u32 dsim_plltmr;
70 	u32 dsim_phyacchr;
71 	u32 dsim_phyacchr1;
72 
73 	u32 __reserved4[(0x2000 - 0x015C) / 4];
74 	u32 mipi_csis_pktdata[0x2000 / 4];
75 };
76 
77 enum nx_mipi_dsi_syncmode {
78 	nx_mipi_dsi_syncmode_event = 0,
79 	nx_mipi_dsi_syncmode_pulse = 1,
80 };
81 
82 enum nx_mipi_dsi_format {
83 	nx_mipi_dsi_format_command3 = 0,
84 	nx_mipi_dsi_format_command8 = 1,
85 	nx_mipi_dsi_format_command12 = 2,
86 	nx_mipi_dsi_format_command16 = 3,
87 	nx_mipi_dsi_format_rgb565 = 4,
88 	nx_mipi_dsi_format_rgb666_packed = 5,
89 	nx_mipi_dsi_format_rgb666 = 6,
90 	nx_mipi_dsi_format_rgb888 = 7
91 };
92 
93 enum nx_mipi_dsi_lpmode {
94 	nx_mipi_dsi_lpmode_hs = 0,
95 	nx_mipi_dsi_lpmode_lp = 1
96 };
97 
98 enum nx_mipi_phy_b_dphyctl {
99 	nx_mipi_phy_b_dphyctl_m_txclkesc_20_mhz = 0x1F4,
100 	nx_mipi_phy_b_dphyctl_m_txclkesc_19_mhz = 0x1DB,
101 	nx_mipi_phy_b_dphyctl_m_txclkesc_18_mhz = 0x1C2,
102 	nx_mipi_phy_b_dphyctl_m_txclkesc_17_mhz = 0x1A9,
103 	nx_mipi_phy_b_dphyctl_m_txclkesc_16_mhz = 0x190,
104 	nx_mipi_phy_b_dphyctl_m_txclkesc_15_mhz = 0x177,
105 	nx_mipi_phy_b_dphyctl_m_txclkesc_14_mhz = 0x15E,
106 	nx_mipi_phy_b_dphyctl_m_txclkesc_13_mhz = 0x145,
107 	nx_mipi_phy_b_dphyctl_m_txclkesc_12_mhz = 0x12C,
108 	nx_mipi_phy_b_dphyctl_m_txclkesc_11_mhz = 0x113,
109 	nx_mipi_phy_b_dphyctl_m_txclkesc_10_mhz = 0x0FA,
110 	nx_mipi_phy_b_dphyctl_m_txclkesc_9_mhz = 0x0E1,
111 	nx_mipi_phy_b_dphyctl_m_txclkesc_8_mhz = 0x0C8,
112 	nx_mipi_phy_b_dphyctl_m_txclkesc_7_mhz = 0x0AF,
113 	nx_mipi_phy_b_dphyctl_m_txclkesc_6_mhz = 0x096,
114 	nx_mipi_phy_b_dphyctl_m_txclkesc_5_mhz = 0x07D,
115 	nx_mipi_phy_b_dphyctl_m_txclkesc_4_mhz = 0x064,
116 	nx_mipi_phy_b_dphyctl_m_txclkesc_3_mhz = 0x04B,
117 	nx_mipi_phy_b_dphyctl_m_txclkesc_2_mhz = 0x032,
118 	nx_mipi_phy_b_dphyctl_m_txclkesc_1_mhz = 0x019,
119 	nx_mipi_phy_b_dphyctl_m_txclkesc_0_10_mhz = 0x003,
120 	nx_mipi_phy_b_dphyctl_m_txclkesc_0_01_mhz = 0x000
121 };
122 
123 enum {
124 	nx_mipi_rst = 0,
125 	nx_mipi_rst_dsi_i,
126 	nx_mipi_rst_csi_i,
127 	nx_mipi_rst_phy_s,
128 	nx_mipi_rst_phy_m
129 };
130 
131 enum nx_mipi_int {
132 	nx_mipi_int_csi_even_before = 31,
133 	nx_mipi_int_csi_even_after = 30,
134 	nx_mipi_int_csi_odd_before = 29,
135 	nx_mipi_int_csi_odd_after = 28,
136 	nx_mipi_int_csi_frame_start_ch3 = 27,
137 	nx_mipi_int_csi_frame_start_ch2 = 26,
138 	nx_mipi_int_csi_frame_start_ch1 = 25,
139 	nx_mipi_int_csi_frame_start_ch0 = 24,
140 	nx_mipi_int_csi_frame_end_ch3 = 23,
141 	nx_mipi_int_csi_frame_end_ch2 = 22,
142 	nx_mipi_int_csi_frame_end_ch1 = 21,
143 	nx_mipi_int_csi_frame_end_ch0 = 20,
144 	nx_mipi_int_csi_err_sot_hs_ch3 = 19,
145 	nx_mipi_int_csi_err_sot_hs_ch2 = 18,
146 	nx_mipi_int_csi_err_sot_hs_ch1 = 17,
147 	nx_mipi_int_csi_err_sot_hs_ch0 = 16,
148 	nx_mipi_int_csi_err_lost_fs_ch3 = 15,
149 	nx_mipi_int_csi_err_lost_fs_ch2 = 14,
150 	nx_mipi_int_csi_err_lost_fs_ch1 = 13,
151 	nx_mipi_int_csi_err_lost_fs_ch0 = 12,
152 	nx_mipi_int_csi_err_lost_fe_ch3 = 11,
153 	nx_mipi_int_csi_err_lost_fe_ch2 = 10,
154 	nx_mipi_int_csi_err_lost_fe_ch1 = 9,
155 	nx_mipi_int_csi_err_lost_fe_ch0 = 8,
156 	nx_mipi_int_csi_err_over_ch3 = 7,
157 	nx_mipi_int_csi_err_over_ch2 = 6,
158 	nx_mipi_int_csi_err_over_ch1 = 5,
159 	nx_mipi_int_csi_err_over_ch0 = 4,
160 
161 	nx_mipi_int_csi_err_ecc = 2,
162 	nx_mipi_int_csi_err_crc = 1,
163 	nx_mipi_int_csi_err_id = 0,
164 	nx_mipi_int_dsi_pll_stable = 32 + 31,
165 	nx_mipi_int_dsi_sw_rst_release = 32 + 30,
166 	nx_mipi_int_dsi_sfrplfifoempty = 32 + 29,
167 	nx_mipi_int_dsi_sfrphfifoempty = 32 + 28,
168 	nx_mipi_int_dsi_sync_override = 32 + 27,
169 
170 	nx_mipi_int_dsi_bus_turn_over = 32 + 25,
171 	nx_mipi_int_dsi_frame_done = 32 + 24,
172 
173 	nx_mipi_int_dsi_lpdr_tout = 32 + 21,
174 	nx_mipi_int_dsi_ta_tout = 32 + 20,
175 
176 	nx_mipi_int_dsi_rx_dat_done = 32 + 18,
177 	nx_mipi_int_dsi_rx_te = 32 + 17,
178 	nx_mipi_int_dsi_rx_ack = 32 + 16,
179 	nx_mipi_int_dsi_err_rx_ecc = 32 + 15,
180 	nx_mipi_int_dsi_err_rx_crc = 32 + 14,
181 	nx_mipi_int_dsi_err_esc3 = 32 + 13,
182 	nx_mipi_int_dsi_err_esc2 = 32 + 12,
183 	nx_mipi_int_dsi_err_esc1 = 32 + 11,
184 	nx_mipi_int_dsi_err_esc0 = 32 + 10,
185 	nx_mipi_int_dsi_err_sync3 = 32 + 9,
186 	nx_mipi_int_dsi_err_sync2 = 32 + 8,
187 	nx_mipi_int_dsi_err_sync1 = 32 + 7,
188 	nx_mipi_int_dsi_err_sync0 = 32 + 6,
189 	nx_mipi_int_dsi_err_control3 = 32 + 5,
190 	nx_mipi_int_dsi_err_control2 = 32 + 4,
191 	nx_mipi_int_dsi_err_control1 = 32 + 3,
192 	nx_mipi_int_dsi_err_control0 = 32 + 2,
193 	nx_mipi_int_dsi_err_content_lp0 = 32 + 1,
194 	nx_mipi_int_dsi_err_content_lp1 = 32 + 0,
195 };
196 
197 #define DSI_TX_FIFO_SIZE	2048
198 #define DSI_RX_FIFO_SIZE	256
199 #define DSI_RX_FIFO_EMPTY	0x30800002
200 
201 void nx_mipi_dsi_get_status(u32 module_index, u32 *pulps, u32 *pstop,
202 			    u32 *pispllstable, u32 *pisinreset,
203 			    u32 *pisbackward, u32 *pishsclockready);
204 
205 void nx_mipi_dsi_software_reset(u32 module_index);
206 
207 void nx_mipi_dsi_set_clock(u32 module_index, int enable_txhsclock,
208 			   int use_external_clock, int enable_byte_clock,
209 			   int enable_escclock_clock_lane,
210 			   int enable_escclock_data_lane0,
211 			   int enable_escclock_data_lane1,
212 			   int enable_escclock_data_lane2,
213 			   int enable_escclock_data_lane3,
214 			   int enable_escprescaler,
215 			   u32 escprescalervalue);
216 
217 void nx_mipi_dsi_set_timeout(u32 module_index, u32 bta_tout,
218 			     u32 lpdrtout);
219 
220 void nx_mipi_dsi_set_config_video_mode(u32 module_index,
221 				       int enable_auto_flush_main_display_fifo,
222 				       int enable_auto_vertical_count,
223 				       int enable_burst,
224 				       enum nx_mipi_dsi_syncmode
225 				       sync_mode, int enable_eo_tpacket,
226 				       int enable_hsync_end_packet,
227 				       int enable_hfp, int enable_hbp,
228 				       int enable_hsa,
229 				       u32 number_of_virtual_channel,
230 				       enum nx_mipi_dsi_format format,
231 				       u32 number_of_words_in_hfp,
232 				       u32 number_of_words_in_hbp,
233 				       u32 number_of_words_in_hsync,
234 				       u32 number_of_lines_in_vfp,
235 				       u32 number_of_lines_in_vbp,
236 				       u32 number_of_lines_in_vsync,
237 				       u32 number_of_lines_in_command_allow);
238 
239 void nx_mipi_dsi_set_config_command_mode(u32 module_index,
240 					 int enable_auto_flush_main_display_fifo,
241 					 int enable_eo_tpacket,
242 					 u32 number_of_virtual_channel,
243 					 enum nx_mipi_dsi_format format);
244 
245 void nx_mipi_dsi_set_escape_mode(u32 module_index, u32 stop_state_count,
246 				 int force_stop_state, int force_bta,
247 				 enum nx_mipi_dsi_lpmode cmdin_lp,
248 				 enum nx_mipi_dsi_lpmode txinlp);
249 void nx_mipi_dsi_set_escape_lp(u32 module_index,
250 			       enum nx_mipi_dsi_lpmode cmdin_lp,
251 			       enum nx_mipi_dsi_lpmode txinlp);
252 
253 void nx_mipi_dsi_remote_reset_trigger(u32 module_index);
254 void nx_mipi_dsi_set_ulps(u32 module_index, int ulpsclocklane,
255 			  int ulpsdatalane);
256 void nx_mipi_dsi_set_size(u32 module_index, u32 width, u32 height);
257 void nx_mipi_dsi_set_enable(u32 module_index, int enable);
258 void nx_mipi_dsi_set_phy(u32 module_index, u32 number_of_data_lanes,
259 			 int enable_clock_lane, int enable_data_lane0,
260 			 int enable_data_lane1, int enable_data_lane2,
261 			 int enable_data_lane3, int swap_clock_lane,
262 			 int swap_data_lane);
263 
264 void nx_mipi_dsi_set_pll(u32 module_index, int enable,
265 			 u32 pllstabletimer, u32 m_pllpms, u32 m_bandctl,
266 			 u32 m_dphyctl, u32 b_dphyctl);
267 
268 void nx_mipi_dsi_write_pkheader(u32 module_index, u32 data);
269 void nx_mipi_dsi_write_payload(u32 module_index, u32 data);
270 u32 nx_mipi_dsi_read_fifo(u32 module_index);
271 u32 nx_mipi_dsi_read_fifo_status(u32 module_index);
272 
273 int nx_mipi_smoke_test(u32 module_index);
274 void nx_mipi_set_base_address(u32 module_index, void *base_address);
275 void *nx_mipi_get_base_address(u32 module_index);
276 u32 nx_mipi_get_physical_address(u32 module_index);
277 
278 void nx_mipi_dsi_set_interrupt_enable_all(u32 module_index, int enable);
279 void nx_mipi_dsi_set_interrupt_enable(u32 module_index,
280 				      u32 int_num, int enable);
281 int nx_mipi_dsi_get_interrupt_enable(u32 module_index, u32 int_num);
282 int nx_mipi_dsi_get_interrupt_enable_all(u32 module_index);
283 
284 int nx_mipi_dsi_get_interrupt_pending(u32 module_index, u32 int_num);
285 int nx_mipi_dsi_get_interrupt_pending_all(u32 module_index);
286 int32_t nx_mipi_dsi_get_interrupt_pending_number(u32 module_index);
287 
288 void nx_mipi_dsi_clear_interrupt_pending(u32 module_index, u32 int_num);
289 void nx_mipi_dsi_clear_interrupt_pending_all(u32 module_index);
290 
291 #endif
292