1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <bootm.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <init.h>
13 #include <log.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <imx_thermal.h>
24 #include <ipu_pixfmt.h>
25 #include <thermal.h>
26 #include <sata.h>
27 #include <dm/device-internal.h>
28 #include <dm/uclass-internal.h>
29
30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h>
32 #endif
33
34 static u32 reset_cause = -1;
35
get_imx_reset_cause(void)36 u32 get_imx_reset_cause(void)
37 {
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
39
40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD)
44 writel(reset_cause, &src_regs->srsr);
45 #endif
46 }
47
48 return reset_cause;
49 }
50
51 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
get_reset_cause(void)52 static char *get_reset_cause(void)
53 {
54 switch (get_imx_reset_cause()) {
55 case 0x00001:
56 case 0x00011:
57 return "POR";
58 case 0x00004:
59 return "CSU";
60 case 0x00008:
61 return "IPP USER";
62 case 0x00010:
63 #ifdef CONFIG_MX7
64 return "WDOG1";
65 #else
66 return "WDOG";
67 #endif
68 case 0x00020:
69 return "JTAG HIGH-Z";
70 case 0x00040:
71 return "JTAG SW";
72 case 0x00080:
73 return "WDOG3";
74 #ifdef CONFIG_MX7
75 case 0x00100:
76 return "WDOG4";
77 case 0x00200:
78 return "TEMPSENSE";
79 #elif defined(CONFIG_IMX8M)
80 case 0x00100:
81 return "WDOG2";
82 case 0x00200:
83 return "TEMPSENSE";
84 #else
85 case 0x00100:
86 return "TEMPSENSE";
87 case 0x10000:
88 return "WARM BOOT";
89 #endif
90 default:
91 return "unknown reset";
92 }
93 }
94 #endif
95
96 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
97
get_imx_type(u32 imxtype)98 const char *get_imx_type(u32 imxtype)
99 {
100 switch (imxtype) {
101 case MXC_CPU_IMX8MP:
102 return "8MP[8]"; /* Quad-core version of the imx8mp */
103 case MXC_CPU_IMX8MPD:
104 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
105 case MXC_CPU_IMX8MPL:
106 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
107 case MXC_CPU_IMX8MP6:
108 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
109 case MXC_CPU_IMX8MN:
110 return "8MNano Quad"; /* Quad-core version */
111 case MXC_CPU_IMX8MND:
112 return "8MNano Dual"; /* Dual-core version */
113 case MXC_CPU_IMX8MNS:
114 return "8MNano Solo"; /* Single-core version */
115 case MXC_CPU_IMX8MNL:
116 return "8MNano QuadLite"; /* Quad-core Lite version */
117 case MXC_CPU_IMX8MNDL:
118 return "8MNano DualLite"; /* Dual-core Lite version */
119 case MXC_CPU_IMX8MNSL:
120 return "8MNano SoloLite"; /* Single-core Lite version */
121 case MXC_CPU_IMX8MM:
122 return "8MMQ"; /* Quad-core version of the imx8mm */
123 case MXC_CPU_IMX8MML:
124 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
125 case MXC_CPU_IMX8MMD:
126 return "8MMD"; /* Dual-core version of the imx8mm */
127 case MXC_CPU_IMX8MMDL:
128 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
129 case MXC_CPU_IMX8MMS:
130 return "8MMS"; /* Single-core version of the imx8mm */
131 case MXC_CPU_IMX8MMSL:
132 return "8MMSL"; /* Single-core Lite version of the imx8mm */
133 case MXC_CPU_IMX8MQ:
134 return "8MQ"; /* Quad-core version of the imx8mq */
135 case MXC_CPU_IMX8MQL:
136 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
137 case MXC_CPU_IMX8MD:
138 return "8MD"; /* Dual-core version of the imx8mq */
139 case MXC_CPU_MX7S:
140 return "7S"; /* Single-core version of the mx7 */
141 case MXC_CPU_MX7D:
142 return "7D"; /* Dual-core version of the mx7 */
143 case MXC_CPU_MX6QP:
144 return "6QP"; /* Quad-Plus version of the mx6 */
145 case MXC_CPU_MX6DP:
146 return "6DP"; /* Dual-Plus version of the mx6 */
147 case MXC_CPU_MX6Q:
148 return "6Q"; /* Quad-core version of the mx6 */
149 case MXC_CPU_MX6D:
150 return "6D"; /* Dual-core version of the mx6 */
151 case MXC_CPU_MX6DL:
152 return "6DL"; /* Dual Lite version of the mx6 */
153 case MXC_CPU_MX6SOLO:
154 return "6SOLO"; /* Solo version of the mx6 */
155 case MXC_CPU_MX6SL:
156 return "6SL"; /* Solo-Lite version of the mx6 */
157 case MXC_CPU_MX6SLL:
158 return "6SLL"; /* SLL version of the mx6 */
159 case MXC_CPU_MX6SX:
160 return "6SX"; /* SoloX version of the mx6 */
161 case MXC_CPU_MX6UL:
162 return "6UL"; /* Ultra-Lite version of the mx6 */
163 case MXC_CPU_MX6ULL:
164 return "6ULL"; /* ULL version of the mx6 */
165 case MXC_CPU_MX6ULZ:
166 return "6ULZ"; /* ULZ version of the mx6 */
167 case MXC_CPU_MX51:
168 return "51";
169 case MXC_CPU_MX53:
170 return "53";
171 default:
172 return "??";
173 }
174 }
175
print_cpuinfo(void)176 int print_cpuinfo(void)
177 {
178 u32 cpurev;
179 __maybe_unused u32 max_freq;
180
181 cpurev = get_cpu_rev();
182
183 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
184 struct udevice *thermal_dev;
185 int cpu_tmp, minc, maxc, ret;
186
187 printf("CPU: Freescale i.MX%s rev%d.%d",
188 get_imx_type((cpurev & 0x1FF000) >> 12),
189 (cpurev & 0x000F0) >> 4,
190 (cpurev & 0x0000F) >> 0);
191 max_freq = get_cpu_speed_grade_hz();
192 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
193 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
194 } else {
195 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
196 mxc_get_clock(MXC_ARM_CLK) / 1000000);
197 }
198 #else
199 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
200 get_imx_type((cpurev & 0x1FF000) >> 12),
201 (cpurev & 0x000F0) >> 4,
202 (cpurev & 0x0000F) >> 0,
203 mxc_get_clock(MXC_ARM_CLK) / 1000000);
204 #endif
205
206 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
207 puts("CPU: ");
208 switch (get_cpu_temp_grade(&minc, &maxc)) {
209 case TEMP_AUTOMOTIVE:
210 puts("Automotive temperature grade ");
211 break;
212 case TEMP_INDUSTRIAL:
213 puts("Industrial temperature grade ");
214 break;
215 case TEMP_EXTCOMMERCIAL:
216 puts("Extended Commercial temperature grade ");
217 break;
218 default:
219 puts("Commercial temperature grade ");
220 break;
221 }
222 printf("(%dC to %dC)", minc, maxc);
223 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
224 if (!ret) {
225 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
226
227 if (!ret)
228 printf(" at %dC", cpu_tmp);
229 else
230 debug(" - invalid sensor data\n");
231 } else {
232 debug(" - invalid sensor device\n");
233 }
234 puts("\n");
235 #endif
236
237 printf("Reset cause: %s\n", get_reset_cause());
238 return 0;
239 }
240 #endif
241
cpu_eth_init(struct bd_info * bis)242 int cpu_eth_init(struct bd_info *bis)
243 {
244 int rc = -ENODEV;
245
246 #if defined(CONFIG_FEC_MXC)
247 rc = fecmxc_initialize(bis);
248 #endif
249
250 return rc;
251 }
252
253 #ifdef CONFIG_FSL_ESDHC_IMX
254 /*
255 * Initializes on-chip MMC controllers.
256 * to override, implement board_mmc_init()
257 */
cpu_mmc_init(struct bd_info * bis)258 int cpu_mmc_init(struct bd_info *bis)
259 {
260 return fsl_esdhc_mmc_init(bis);
261 }
262 #endif
263
264 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
get_ahb_clk(void)265 u32 get_ahb_clk(void)
266 {
267 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
268 u32 reg, ahb_podf;
269
270 reg = __raw_readl(&imx_ccm->cbcdr);
271 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
272 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
273
274 return get_periph_clk() / (ahb_podf + 1);
275 }
276 #endif
277
arch_preboot_os(void)278 void arch_preboot_os(void)
279 {
280 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
281 imx_pcie_remove();
282 #endif
283
284 #if defined(CONFIG_IMX_AHCI)
285 struct udevice *dev;
286 int rc;
287
288 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
289 if (!rc && dev) {
290 rc = device_remove(dev, DM_REMOVE_NORMAL);
291 if (rc)
292 printf("Cannot remove SATA device '%s' (err=%d)\n",
293 dev->name, rc);
294 }
295 #endif
296
297 #if defined(CONFIG_SATA)
298 if (!is_mx6sdl()) {
299 sata_remove(0);
300 #if defined(CONFIG_MX6)
301 disable_sata_clock();
302 #endif
303 }
304 #endif
305 #if defined(CONFIG_VIDEO_IPUV3)
306 /* disable video before launching O/S */
307 ipuv3_fb_shutdown();
308 #endif
309 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
310 lcdif_power_down();
311 #endif
312 }
313
314 #ifndef CONFIG_IMX8M
set_chipselect_size(int const cs_size)315 void set_chipselect_size(int const cs_size)
316 {
317 unsigned int reg;
318 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
319 reg = readl(&iomuxc_regs->gpr[1]);
320
321 switch (cs_size) {
322 case CS0_128:
323 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
324 reg |= 0x5;
325 break;
326 case CS0_64M_CS1_64M:
327 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
328 reg |= 0x1B;
329 break;
330 case CS0_64M_CS1_32M_CS2_32M:
331 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
332 reg |= 0x4B;
333 break;
334 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
335 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
336 reg |= 0x249;
337 break;
338 default:
339 printf("Unknown chip select size: %d\n", cs_size);
340 break;
341 }
342
343 writel(reg, &iomuxc_regs->gpr[1]);
344 }
345 #endif
346
347 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
348 /*
349 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
350 * defines a 2-bit SPEED_GRADING
351 */
352 #define OCOTP_TESTER3_SPEED_SHIFT 8
353 enum cpu_speed {
354 OCOTP_TESTER3_SPEED_GRADE0,
355 OCOTP_TESTER3_SPEED_GRADE1,
356 OCOTP_TESTER3_SPEED_GRADE2,
357 OCOTP_TESTER3_SPEED_GRADE3,
358 OCOTP_TESTER3_SPEED_GRADE4,
359 };
360
get_cpu_speed_grade_hz(void)361 u32 get_cpu_speed_grade_hz(void)
362 {
363 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
364 struct fuse_bank *bank = &ocotp->bank[1];
365 struct fuse_bank1_regs *fuse =
366 (struct fuse_bank1_regs *)bank->fuse_regs;
367 uint32_t val;
368
369 val = readl(&fuse->tester3);
370 val >>= OCOTP_TESTER3_SPEED_SHIFT;
371
372 if (is_imx8mn() || is_imx8mp()) {
373 val &= 0xf;
374 return 2300000000 - val * 100000000;
375 }
376
377 if (is_imx8mm())
378 val &= 0x7;
379 else
380 val &= 0x3;
381
382 switch(val) {
383 case OCOTP_TESTER3_SPEED_GRADE0:
384 return 800000000;
385 case OCOTP_TESTER3_SPEED_GRADE1:
386 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
387 case OCOTP_TESTER3_SPEED_GRADE2:
388 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
389 case OCOTP_TESTER3_SPEED_GRADE3:
390 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
391 case OCOTP_TESTER3_SPEED_GRADE4:
392 return 2000000000;
393 }
394
395 return 0;
396 }
397
398 /*
399 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
400 * defines a 2-bit SPEED_GRADING
401 */
402 #define OCOTP_TESTER3_TEMP_SHIFT 6
403
404 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
405 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
406
get_cpu_temp_grade(int * minc,int * maxc)407 u32 get_cpu_temp_grade(int *minc, int *maxc)
408 {
409 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
410 struct fuse_bank *bank = &ocotp->bank[1];
411 struct fuse_bank1_regs *fuse =
412 (struct fuse_bank1_regs *)bank->fuse_regs;
413 uint32_t val;
414
415 val = readl(&fuse->tester3);
416 if (is_imx8mp())
417 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
418 else
419 val >>= OCOTP_TESTER3_TEMP_SHIFT;
420 val &= 0x3;
421
422 if (minc && maxc) {
423 if (val == TEMP_AUTOMOTIVE) {
424 *minc = -40;
425 *maxc = 125;
426 } else if (val == TEMP_INDUSTRIAL) {
427 *minc = -40;
428 *maxc = 105;
429 } else if (val == TEMP_EXTCOMMERCIAL) {
430 *minc = -20;
431 *maxc = 105;
432 } else {
433 *minc = 0;
434 *maxc = 95;
435 }
436 }
437 return val;
438 }
439 #endif
440
441 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
get_boot_device(void)442 enum boot_device get_boot_device(void)
443 {
444 struct bootrom_sw_info **p =
445 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
446
447 enum boot_device boot_dev = SD1_BOOT;
448 u8 boot_type = (*p)->boot_dev_type;
449 u8 boot_instance = (*p)->boot_dev_instance;
450
451 switch (boot_type) {
452 case BOOT_TYPE_SD:
453 boot_dev = boot_instance + SD1_BOOT;
454 break;
455 case BOOT_TYPE_MMC:
456 boot_dev = boot_instance + MMC1_BOOT;
457 break;
458 case BOOT_TYPE_NAND:
459 boot_dev = NAND_BOOT;
460 break;
461 case BOOT_TYPE_QSPI:
462 boot_dev = QSPI_BOOT;
463 break;
464 case BOOT_TYPE_WEIM:
465 boot_dev = WEIM_NOR_BOOT;
466 break;
467 case BOOT_TYPE_SPINOR:
468 boot_dev = SPI_NOR_BOOT;
469 break;
470 case BOOT_TYPE_USB:
471 boot_dev = USB_BOOT;
472 break;
473 default:
474 #ifdef CONFIG_IMX8M
475 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
476 boot_dev = QSPI_BOOT;
477 #endif
478 break;
479 }
480
481 return boot_dev;
482 }
483 #endif
484
485 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)486 int nxp_board_rev(void)
487 {
488 /*
489 * Get Board ID information from OCOTP_GP1[15:8]
490 * RevA: 0x1
491 * RevB: 0x2
492 * RevC: 0x3
493 */
494 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
495 struct fuse_bank *bank = &ocotp->bank[4];
496 struct fuse_bank4_regs *fuse =
497 (struct fuse_bank4_regs *)bank->fuse_regs;
498
499 return (readl(&fuse->gp1) >> 8 & 0x0F);
500 }
501
nxp_board_rev_string(void)502 char nxp_board_rev_string(void)
503 {
504 const char *rev = "A";
505
506 return (*rev + nxp_board_rev() - 1);
507 }
508 #endif
509