1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 #define MAX_PIPES 6 39 #define MAX_DIG_LINK_ENCODERS 7 40 #define MAX_DWB_PIPES 1 41 #if defined(CONFIG_DRM_AMD_DC_DCN) 42 #define MAX_HPO_DP2_ENCODERS 4 43 #define MAX_HPO_DP2_LINK_ENCODERS 2 44 #endif 45 46 struct gamma_curve { 47 uint32_t offset; 48 uint32_t segments_num; 49 }; 50 51 struct curve_points { 52 struct fixed31_32 x; 53 struct fixed31_32 y; 54 struct fixed31_32 offset; 55 struct fixed31_32 slope; 56 57 uint32_t custom_float_x; 58 uint32_t custom_float_y; 59 uint32_t custom_float_offset; 60 uint32_t custom_float_slope; 61 }; 62 63 struct curve_points3 { 64 struct curve_points red; 65 struct curve_points green; 66 struct curve_points blue; 67 }; 68 69 struct pwl_result_data { 70 struct fixed31_32 red; 71 struct fixed31_32 green; 72 struct fixed31_32 blue; 73 74 struct fixed31_32 delta_red; 75 struct fixed31_32 delta_green; 76 struct fixed31_32 delta_blue; 77 78 uint32_t red_reg; 79 uint32_t green_reg; 80 uint32_t blue_reg; 81 82 uint32_t delta_red_reg; 83 uint32_t delta_green_reg; 84 uint32_t delta_blue_reg; 85 }; 86 87 struct dc_rgb { 88 uint32_t red; 89 uint32_t green; 90 uint32_t blue; 91 }; 92 93 struct tetrahedral_17x17x17 { 94 struct dc_rgb lut0[1229]; 95 struct dc_rgb lut1[1228]; 96 struct dc_rgb lut2[1228]; 97 struct dc_rgb lut3[1228]; 98 }; 99 struct tetrahedral_9x9x9 { 100 struct dc_rgb lut0[183]; 101 struct dc_rgb lut1[182]; 102 struct dc_rgb lut2[182]; 103 struct dc_rgb lut3[182]; 104 }; 105 106 struct tetrahedral_params { 107 union { 108 struct tetrahedral_17x17x17 tetrahedral_17; 109 struct tetrahedral_9x9x9 tetrahedral_9; 110 }; 111 bool use_tetrahedral_9; 112 bool use_12bits; 113 114 }; 115 116 /* arr_curve_points - regamma regions/segments specification 117 * arr_points - beginning and end point specified separately (only one on DCE) 118 * corner_points - beginning and end point for all 3 colors (DCN) 119 * rgb_resulted - final curve 120 */ 121 struct pwl_params { 122 struct gamma_curve arr_curve_points[34]; 123 union { 124 struct curve_points arr_points[2]; 125 struct curve_points3 corner_points[2]; 126 }; 127 struct pwl_result_data rgb_resulted[256 + 3]; 128 uint32_t hw_points_num; 129 }; 130 131 /* move to dpp 132 * while we are moving functionality out of opp to dpp to align 133 * HW programming to HW IP, we define these struct in hw_shared 134 * so we can still compile while refactoring 135 */ 136 137 enum lb_pixel_depth { 138 /* do not change the values because it is used as bit vector */ 139 LB_PIXEL_DEPTH_18BPP = 1, 140 LB_PIXEL_DEPTH_24BPP = 2, 141 LB_PIXEL_DEPTH_30BPP = 4, 142 LB_PIXEL_DEPTH_36BPP = 8 143 }; 144 145 enum graphics_csc_adjust_type { 146 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 147 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 148 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 149 }; 150 151 enum ipp_degamma_mode { 152 IPP_DEGAMMA_MODE_BYPASS, 153 IPP_DEGAMMA_MODE_HW_sRGB, 154 IPP_DEGAMMA_MODE_HW_xvYCC, 155 IPP_DEGAMMA_MODE_USER_PWL 156 }; 157 158 enum gamcor_mode { 159 GAMCOR_MODE_BYPASS, 160 GAMCOR_MODE_RESERVED_1, 161 GAMCOR_MODE_USER_PWL, 162 GAMCOR_MODE_RESERVED_3 163 }; 164 165 enum ipp_output_format { 166 IPP_OUTPUT_FORMAT_12_BIT_FIX, 167 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 168 IPP_OUTPUT_FORMAT_FLOAT 169 }; 170 171 enum expansion_mode { 172 EXPANSION_MODE_DYNAMIC, 173 EXPANSION_MODE_ZERO 174 }; 175 176 struct default_adjustment { 177 enum lb_pixel_depth lb_color_depth; 178 enum dc_color_space out_color_space; 179 enum dc_color_space in_color_space; 180 enum dc_color_depth color_depth; 181 enum pixel_format surface_pixel_format; 182 enum graphics_csc_adjust_type csc_adjust_type; 183 bool force_hw_default; 184 }; 185 186 187 struct out_csc_color_matrix { 188 enum dc_color_space color_space; 189 uint16_t regval[12]; 190 }; 191 192 enum gamut_remap_select { 193 GAMUT_REMAP_BYPASS = 0, 194 GAMUT_REMAP_COEFF, 195 GAMUT_REMAP_COMA_COEFF, 196 GAMUT_REMAP_COMB_COEFF 197 }; 198 199 enum opp_regamma { 200 OPP_REGAMMA_BYPASS = 0, 201 OPP_REGAMMA_SRGB, 202 OPP_REGAMMA_XVYCC, 203 OPP_REGAMMA_USER 204 }; 205 206 enum optc_dsc_mode { 207 OPTC_DSC_DISABLED = 0, 208 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 209 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 210 }; 211 212 struct dc_bias_and_scale { 213 uint16_t scale_red; 214 uint16_t bias_red; 215 uint16_t scale_green; 216 uint16_t bias_green; 217 uint16_t scale_blue; 218 uint16_t bias_blue; 219 }; 220 221 enum test_pattern_dyn_range { 222 TEST_PATTERN_DYN_RANGE_VESA = 0, 223 TEST_PATTERN_DYN_RANGE_CEA 224 }; 225 226 enum test_pattern_mode { 227 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 228 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 229 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 230 TEST_PATTERN_MODE_VERTICALBARS, 231 TEST_PATTERN_MODE_HORIZONTALBARS, 232 TEST_PATTERN_MODE_SINGLERAMP_RGB, 233 TEST_PATTERN_MODE_DUALRAMP_RGB, 234 TEST_PATTERN_MODE_XR_BIAS_RGB 235 }; 236 237 enum test_pattern_color_format { 238 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 239 TEST_PATTERN_COLOR_FORMAT_BPC_8, 240 TEST_PATTERN_COLOR_FORMAT_BPC_10, 241 TEST_PATTERN_COLOR_FORMAT_BPC_12 242 }; 243 244 enum controller_dp_test_pattern { 245 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 246 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 247 CONTROLLER_DP_TEST_PATTERN_PRBS7, 248 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 249 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 250 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 251 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 252 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 253 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 254 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 255 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 256 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 257 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 258 }; 259 260 enum controller_dp_color_space { 261 CONTROLLER_DP_COLOR_SPACE_RGB, 262 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 263 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 264 CONTROLLER_DP_COLOR_SPACE_UDEFINED 265 }; 266 267 enum dc_lut_mode { 268 LUT_BYPASS, 269 LUT_RAM_A, 270 LUT_RAM_B 271 }; 272 273 /** 274 * speakersToChannels 275 * 276 * @brief 277 * translate speakers to channels 278 * 279 * FL - Front Left 280 * FR - Front Right 281 * RL - Rear Left 282 * RR - Rear Right 283 * RC - Rear Center 284 * FC - Front Center 285 * FLC - Front Left Center 286 * FRC - Front Right Center 287 * RLC - Rear Left Center 288 * RRC - Rear Right Center 289 * LFE - Low Freq Effect 290 * 291 * FC 292 * FLC FRC 293 * FL FR 294 * 295 * LFE 296 * () 297 * 298 * 299 * RL RR 300 * RLC RRC 301 * RC 302 * 303 * ch 8 7 6 5 4 3 2 1 304 * 0b00000011 - - - - - - FR FL 305 * 0b00000111 - - - - - LFE FR FL 306 * 0b00001011 - - - - FC - FR FL 307 * 0b00001111 - - - - FC LFE FR FL 308 * 0b00010011 - - - RC - - FR FL 309 * 0b00010111 - - - RC - LFE FR FL 310 * 0b00011011 - - - RC FC - FR FL 311 * 0b00011111 - - - RC FC LFE FR FL 312 * 0b00110011 - - RR RL - - FR FL 313 * 0b00110111 - - RR RL - LFE FR FL 314 * 0b00111011 - - RR RL FC - FR FL 315 * 0b00111111 - - RR RL FC LFE FR FL 316 * 0b01110011 - RC RR RL - - FR FL 317 * 0b01110111 - RC RR RL - LFE FR FL 318 * 0b01111011 - RC RR RL FC - FR FL 319 * 0b01111111 - RC RR RL FC LFE FR FL 320 * 0b11110011 RRC RLC RR RL - - FR FL 321 * 0b11110111 RRC RLC RR RL - LFE FR FL 322 * 0b11111011 RRC RLC RR RL FC - FR FL 323 * 0b11111111 RRC RLC RR RL FC LFE FR FL 324 * 0b11000011 FRC FLC - - - - FR FL 325 * 0b11000111 FRC FLC - - - LFE FR FL 326 * 0b11001011 FRC FLC - - FC - FR FL 327 * 0b11001111 FRC FLC - - FC LFE FR FL 328 * 0b11010011 FRC FLC - RC - - FR FL 329 * 0b11010111 FRC FLC - RC - LFE FR FL 330 * 0b11011011 FRC FLC - RC FC - FR FL 331 * 0b11011111 FRC FLC - RC FC LFE FR FL 332 * 0b11110011 FRC FLC RR RL - - FR FL 333 * 0b11110111 FRC FLC RR RL - LFE FR FL 334 * 0b11111011 FRC FLC RR RL FC - FR FL 335 * 0b11111111 FRC FLC RR RL FC LFE FR FL 336 * 337 * @param 338 * speakers - speaker information as it comes from CEA audio block 339 */ 340 /* translate speakers to channels */ 341 342 union audio_cea_channels { 343 uint8_t all; 344 struct audio_cea_channels_bits { 345 uint32_t FL:1; 346 uint32_t FR:1; 347 uint32_t LFE:1; 348 uint32_t FC:1; 349 uint32_t RL_RC:1; 350 uint32_t RR:1; 351 uint32_t RC_RLC_FLC:1; 352 uint32_t RRC_FRC:1; 353 } channels; 354 }; 355 356 #endif /* __DAL_HW_SHARED_H__ */ 357