1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <arch_helpers.h>
11 #include <bl31/bl31.h>
12 #include <bl31/interrupt_mgmt.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/ep_info.h>
16 #include <common/interrupt_props.h>
17 #include <context.h>
18 #include <cortex_a57.h>
19 #include <denver.h>
20 #include <drivers/arm/gic_common.h>
21 #include <drivers/arm/gicv2.h>
22 #include <drivers/console.h>
23 #include <lib/el3_runtime/context_mgmt.h>
24 #include <lib/utils.h>
25 #include <lib/xlat_tables/xlat_tables_v2.h>
26 #include <plat/common/platform.h>
27
28 #include <mce.h>
29 #include <memctrl.h>
30 #include <smmu.h>
31 #include <tegra_def.h>
32 #include <tegra_platform.h>
33 #include <tegra_private.h>
34
35 extern void memcpy16(void *dest, const void *src, unsigned int length);
36
37 /*******************************************************************************
38 * Tegra186 CPU numbers in cluster #0
39 *******************************************************************************
40 */
41 #define TEGRA186_CLUSTER0_CORE2 2U
42 #define TEGRA186_CLUSTER0_CORE3 3U
43
44 /*******************************************************************************
45 * The Tegra power domain tree has a single system level power domain i.e. a
46 * single root node. The first entry in the power domain descriptor specifies
47 * the number of power domains at the highest power level.
48 *******************************************************************************
49 */
50 static const uint8_t tegra_power_domain_tree_desc[] = {
51 /* No of root nodes */
52 1,
53 /* No of clusters */
54 PLATFORM_CLUSTER_COUNT,
55 /* No of CPU cores - cluster0 */
56 PLATFORM_MAX_CPUS_PER_CLUSTER,
57 /* No of CPU cores - cluster1 */
58 PLATFORM_MAX_CPUS_PER_CLUSTER
59 };
60
61 /*******************************************************************************
62 * This function returns the Tegra default topology tree information.
63 ******************************************************************************/
plat_get_power_domain_tree_desc(void)64 const uint8_t *plat_get_power_domain_tree_desc(void)
65 {
66 return tegra_power_domain_tree_desc;
67 }
68
69 /*
70 * Table of regions to map using the MMU.
71 */
72 static const mmap_region_t tegra_mmap[] = {
73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
74 MT_DEVICE | MT_RW | MT_SECURE),
75 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
76 MT_DEVICE | MT_RW | MT_SECURE),
77 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
78 MT_DEVICE | MT_RW | MT_SECURE),
79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
80 MT_DEVICE | MT_RW | MT_SECURE),
81 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
82 MT_DEVICE | MT_RW | MT_SECURE),
83 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
84 MT_DEVICE | MT_RW | MT_SECURE),
85 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
86 MT_DEVICE | MT_RW | MT_SECURE),
87 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
88 MT_DEVICE | MT_RW | MT_SECURE),
89 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
90 MT_DEVICE | MT_RW | MT_SECURE),
91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
92 MT_DEVICE | MT_RW | MT_SECURE),
93 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
94 MT_DEVICE | MT_RW | MT_SECURE),
95 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
96 MT_DEVICE | MT_RW | MT_SECURE),
97 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
98 MT_DEVICE | MT_RW | MT_SECURE),
99 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
100 MT_DEVICE | MT_RW | MT_SECURE),
101 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
102 MT_DEVICE | MT_RO | MT_SECURE),
103 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
104 MT_DEVICE | MT_RW | MT_SECURE),
105 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
106 MT_DEVICE | MT_RW | MT_SECURE),
107 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
108 MT_DEVICE | MT_RW | MT_SECURE),
109 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
110 MT_DEVICE | MT_RW | MT_SECURE),
111 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
112 MT_DEVICE | MT_RW | MT_SECURE),
113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
114 MT_DEVICE | MT_RW | MT_SECURE),
115 MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
116 MT_DEVICE | MT_RW | MT_SECURE),
117 {0}
118 };
119
120 /*******************************************************************************
121 * Set up the pagetables as per the platform memory map & initialize the MMU
122 ******************************************************************************/
plat_get_mmio_map(void)123 const mmap_region_t *plat_get_mmio_map(void)
124 {
125 /* MMIO space */
126 return tegra_mmap;
127 }
128
129 /*******************************************************************************
130 * Handler to get the System Counter Frequency
131 ******************************************************************************/
plat_get_syscnt_freq2(void)132 uint32_t plat_get_syscnt_freq2(void)
133 {
134 return 31250000;
135 }
136
137 /*******************************************************************************
138 * Maximum supported UART controllers
139 ******************************************************************************/
140 #define TEGRA186_MAX_UART_PORTS 7
141
142 /*******************************************************************************
143 * This variable holds the UART port base addresses
144 ******************************************************************************/
145 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
146 0, /* undefined - treated as an error case */
147 TEGRA_UARTA_BASE,
148 TEGRA_UARTB_BASE,
149 TEGRA_UARTC_BASE,
150 TEGRA_UARTD_BASE,
151 TEGRA_UARTE_BASE,
152 TEGRA_UARTF_BASE,
153 TEGRA_UARTG_BASE,
154 };
155
156 /*******************************************************************************
157 * Enable console corresponding to the console ID
158 ******************************************************************************/
plat_enable_console(int32_t id)159 void plat_enable_console(int32_t id)
160 {
161 static console_t uart_console;
162 uint32_t console_clock;
163
164 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
165 /*
166 * Reference clock used by the FPGAs is a lot slower.
167 */
168 if (tegra_platform_is_fpga()) {
169 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
170 } else {
171 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
172 }
173
174 (void)console_16550_register(tegra186_uart_addresses[id],
175 console_clock,
176 TEGRA_CONSOLE_BAUDRATE,
177 &uart_console);
178 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
179 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
180 }
181 }
182
183 /*******************************************************************************
184 * Handler for early platform setup
185 ******************************************************************************/
plat_early_platform_setup(void)186 void plat_early_platform_setup(void)
187 {
188 uint64_t impl, val;
189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
190 const struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
191
192 /* Verify chip id is t186 */
193 assert(tegra_chipid_is_t186());
194
195 /* sanity check MCE firmware compatibility */
196 mce_verify_firmware_version();
197
198 /*
199 * Do initial security configuration to allow DRAM/device access.
200 */
201 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
202 (uint32_t)plat_params->tzdram_size);
203
204 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
205
206 /*
207 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
208 * A02p and beyond).
209 */
210 if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
211 (impl != (uint64_t)DENVER_IMPL)) {
212
213 val = read_l2ctlr_el1();
214 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
215 write_l2ctlr_el1(val);
216 }
217
218 /*
219 * The previous bootloader might not have placed the BL32 image
220 * inside the TZDRAM. Platform handler to allow relocation of BL32
221 * image to TZDRAM memory. This behavior might change per platform.
222 */
223 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
224 }
225
226 /*******************************************************************************
227 * Handler for late platform setup
228 ******************************************************************************/
plat_late_platform_setup(void)229 void plat_late_platform_setup(void)
230 {
231 ; /* do nothing */
232 }
233
234 /* Secure IRQs for Tegra186 */
235 static const interrupt_prop_t tegra186_interrupt_props[] = {
236 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
238 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
240 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
242 };
243
244 /*******************************************************************************
245 * Initialize the GIC and SGIs
246 ******************************************************************************/
plat_gic_setup(void)247 void plat_gic_setup(void)
248 {
249 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
250 tegra_gic_init();
251
252 /*
253 * Initialize the FIQ handler only if the platform supports any
254 * FIQ interrupt sources.
255 */
256 tegra_fiq_handler_setup();
257 }
258
259 /*******************************************************************************
260 * Return pointer to the BL31 params from previous bootloader
261 ******************************************************************************/
plat_get_bl31_params(void)262 struct tegra_bl31_params *plat_get_bl31_params(void)
263 {
264 uint32_t val;
265
266 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
267
268 return (struct tegra_bl31_params *)(uintptr_t)val;
269 }
270
271 /*******************************************************************************
272 * Return pointer to the BL31 platform params from previous bootloader
273 ******************************************************************************/
plat_get_bl31_plat_params(void)274 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
275 {
276 uint32_t val;
277
278 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
279
280 return (plat_params_from_bl2_t *)(uintptr_t)val;
281 }
282
283 /*******************************************************************************
284 * This function implements a part of the critical interface between the psci
285 * generic layer and the platform that allows the former to query the platform
286 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
287 * in case the MPIDR is invalid.
288 ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)289 int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
290 {
291 u_register_t cluster_id, cpu_id, pos;
292 int32_t ret;
293
294 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
295 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
296
297 /*
298 * Validate cluster_id by checking whether it represents
299 * one of the two clusters present on the platform.
300 * Validate cpu_id by checking whether it represents a CPU in
301 * one of the two clusters present on the platform.
302 */
303 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
304 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
305 ret = PSCI_E_NOT_PRESENT;
306 } else {
307 /* calculate the core position */
308 pos = cpu_id + (cluster_id << 2U);
309
310 /* check for non-existent CPUs */
311 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
312 ret = PSCI_E_NOT_PRESENT;
313 } else {
314 ret = (int32_t)pos;
315 }
316 }
317
318 return ret;
319 }
320
321 /*******************************************************************************
322 * Handler to relocate BL32 image to TZDRAM
323 ******************************************************************************/
plat_relocate_bl32_image(const image_info_t * bl32_img_info)324 void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
325 {
326 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
327 const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
328 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
329
330 if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
331
332 /* Relocate BL32 if it resides outside of the TZDRAM */
333 tzdram_start = plat_bl31_params->tzdram_base;
334 tzdram_end = plat_bl31_params->tzdram_base +
335 plat_bl31_params->tzdram_size;
336 bl32_start = bl32_img_info->image_base;
337 bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
338
339 assert(tzdram_end > tzdram_start);
340 assert(bl32_end > bl32_start);
341 assert(bl32_ep_info->pc > tzdram_start);
342 assert(bl32_ep_info->pc < tzdram_end);
343
344 /* relocate BL32 */
345 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
346
347 INFO("Relocate BL32 to TZDRAM\n");
348
349 (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
350 (void *)(uintptr_t)bl32_start,
351 bl32_img_info->image_size);
352
353 /* clean up non-secure intermediate buffer */
354 zeromem((void *)(uintptr_t)bl32_start,
355 bl32_img_info->image_size);
356 }
357 }
358 }
359
360 /*******************************************************************************
361 * Handler to indicate support for System Suspend
362 ******************************************************************************/
plat_supports_system_suspend(void)363 bool plat_supports_system_suspend(void)
364 {
365 return true;
366 }
367 /*******************************************************************************
368 * Platform specific runtime setup.
369 ******************************************************************************/
plat_runtime_setup(void)370 void plat_runtime_setup(void)
371 {
372 /*
373 * During cold boot, it is observed that the arbitration
374 * bit is set in the Memory controller leading to false
375 * error interrupts in the non-secure world. To avoid
376 * this, clean the interrupt status register before
377 * booting into the non-secure world
378 */
379 tegra_memctrl_clear_pending_interrupts();
380
381 /*
382 * During boot, USB3 and flash media (SDMMC/SATA) devices need
383 * access to IRAM. Because these clients connect to the MC and
384 * do not have a direct path to the IRAM, the MC implements AHB
385 * redirection during boot to allow path to IRAM. In this mode
386 * accesses to a programmed memory address aperture are directed
387 * to the AHB bus, allowing access to the IRAM. This mode must be
388 * disabled before we jump to the non-secure world.
389 */
390 tegra_memctrl_disable_ahb_redirection();
391
392 /*
393 * Verify the integrity of the previously configured SMMU(s)
394 * settings
395 */
396 tegra_smmu_verify();
397 }
398