1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch.h>
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_tables_v2.h>
18
19 #include <k3_console.h>
20 #include <k3_gicv3.h>
21 #include <ti_sci.h>
22
23 /* Table of regions to map using the MMU */
24 const mmap_region_t plat_k3_mmap[] = {
25 MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
27 MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
28 MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31 { /* sentinel */ }
32 };
33
34 /*
35 * Placeholder variables for maintaining information about the next image(s)
36 */
37 static entry_point_info_t bl32_image_ep_info;
38 static entry_point_info_t bl33_image_ep_info;
39
40 /*******************************************************************************
41 * Gets SPSR for BL33 entry
42 ******************************************************************************/
k3_get_spsr_for_bl33_entry(void)43 static uint32_t k3_get_spsr_for_bl33_entry(void)
44 {
45 unsigned long el_status;
46 unsigned int mode;
47 uint32_t spsr;
48
49 /* Figure out what mode we enter the non-secure world in */
50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
51 el_status &= ID_AA64PFR0_ELX_MASK;
52
53 mode = (el_status) ? MODE_EL2 : MODE_EL1;
54
55 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
56 return spsr;
57 }
58
59 /*******************************************************************************
60 * Perform any BL3-1 early platform setup, such as console init and deciding on
61 * memory layout.
62 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
64 u_register_t arg2, u_register_t arg3)
65 {
66 /* There are no parameters from BL2 if BL31 is a reset vector */
67 assert(arg0 == 0U);
68 assert(arg1 == 0U);
69
70 bl31_console_setup();
71
72 #ifdef BL32_BASE
73 /* Populate entry point information for BL32 */
74 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
75 bl32_image_ep_info.pc = BL32_BASE;
76 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
77 DISABLE_ALL_EXCEPTIONS);
78 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
79 #endif
80
81 /* Populate entry point information for BL33 */
82 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
83 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
84 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
85 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
86
87 #ifdef K3_HW_CONFIG_BASE
88 /*
89 * According to the file ``Documentation/arm64/booting.txt`` of the
90 * Linux kernel tree, Linux expects the physical address of the device
91 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
92 * must be 0.
93 */
94 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
95 bl33_image_ep_info.args.arg1 = 0U;
96 bl33_image_ep_info.args.arg2 = 0U;
97 bl33_image_ep_info.args.arg3 = 0U;
98 #endif
99 }
100
bl31_plat_arch_setup(void)101 void bl31_plat_arch_setup(void)
102 {
103 const mmap_region_t bl_regions[] = {
104 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
105 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
106 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
107 #if USE_COHERENT_MEM
108 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE),
109 #endif
110 { /* sentinel */ }
111 };
112
113 setup_page_tables(bl_regions, plat_k3_mmap);
114 enable_mmu_el3(0);
115 }
116
bl31_platform_setup(void)117 void bl31_platform_setup(void)
118 {
119 k3_gic_driver_init(K3_GIC_BASE);
120 k3_gic_init();
121
122 ti_sci_init();
123 }
124
platform_mem_init(void)125 void platform_mem_init(void)
126 {
127 /* Do nothing for now... */
128 }
129
plat_get_syscnt_freq2(void)130 unsigned int plat_get_syscnt_freq2(void)
131 {
132 uint32_t gtc_freq;
133 uint32_t gtc_ctrl;
134
135 /* Lets try and provide basic diagnostics - cost is low */
136 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
137 /* Did the bootloader fail to enable timer and OS guys are confused? */
138 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
139 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
140 }
141 /*
142 * If debug will not pause time, we will have issues like
143 * drivers timing out while debugging, in cases of OS like Linux,
144 * RCU stall errors, which can be hard to differentiate vs real issues.
145 */
146 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
147 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
148 }
149
150 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
151 /* Many older bootloaders may have missed programming FID0 register */
152 if (gtc_freq != 0U) {
153 return gtc_freq;
154 }
155
156 /*
157 * We could have just warned about this, but this can have serious
158 * hard to debug side effects if we are NOT sure what the actual
159 * frequency is. Lets make sure people don't miss this.
160 */
161 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
162 SYS_COUNTER_FREQ_IN_TICKS);
163
164 return SYS_COUNTER_FREQ_IN_TICKS;
165 }
166
167 /*
168 * Empty function to prevent the console from being uninitialized after BL33 is
169 * started and allow us to see messages from BL31.
170 */
bl31_plat_runtime_setup(void)171 void bl31_plat_runtime_setup(void)
172 {
173 }
174
175 /*******************************************************************************
176 * Return a pointer to the 'entry_point_info' structure of the next image
177 * for the security state specified. BL3-3 corresponds to the non-secure
178 * image type while BL3-2 corresponds to the secure image type. A NULL
179 * pointer is returned if the image does not exist.
180 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)181 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
182 {
183 entry_point_info_t *next_image_info;
184
185 assert(sec_state_is_valid(type));
186 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
187 &bl32_image_ep_info;
188 /*
189 * None of the images on the ARM development platforms can have 0x0
190 * as the entrypoint
191 */
192 if (next_image_info->pc)
193 return next_image_info;
194
195 NOTICE("Requested nonexistent image\n");
196 return NULL;
197 }
198