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Searched defs:pll_settings (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dclock_source.h106 struct pll_settings { struct
107 uint32_t actual_pix_clk_100hz;
108 uint32_t adjusted_pix_clk_100hz;
110 uint32_t vco_freq;
111 uint32_t reference_freq;
112 uint32_t reference_divider;
113 uint32_t feedback_divider;
114 uint32_t fract_feedback_divider;
115 uint32_t pix_clk_post_divider;
116 uint32_t ss_percentage;
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A Dcore_types.h367 struct pll_settings pll_settings; member
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.c195 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance()
251 struct pll_settings *pll_settings, in calc_pll_dividers_in_range()
293 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers()
397 struct pll_settings *pll_settings) in pll_adjust_pix_clk()
475 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper()
537 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper()
567 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers()
600 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers()
843 struct pll_settings *pll_settings) in dce110_program_pix_clk()
916 struct pll_settings *pll_settings) in dce112_program_pix_clk()
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