1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <common.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/arch/system_manager.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
14 /*
15 * Configure all the pin muxes
16 */
sysmgr_pinmux_init(void)17 void sysmgr_pinmux_init(void)
18 {
19 populate_sysmgr_pinmux();
20 populate_sysmgr_fpgaintf_module();
21 }
22
23 /*
24 * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
25 * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
26 * CONFIG_SYSMGR_ISWGRP_HANDOFF.
27 */
populate_sysmgr_fpgaintf_module(void)28 void populate_sysmgr_fpgaintf_module(void)
29 {
30 u32 handoff_val = 0;
31
32 /* Enable the signal for those HPS peripherals that use FPGA. */
33 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) ==
34 SYSMGR_FPGAINTF_USEFPGA)
35 handoff_val |= SYSMGR_FPGAINTF_NAND;
36 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) ==
37 SYSMGR_FPGAINTF_USEFPGA)
38 handoff_val |= SYSMGR_FPGAINTF_SDMMC;
39 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) ==
40 SYSMGR_FPGAINTF_USEFPGA)
41 handoff_val |= SYSMGR_FPGAINTF_SPIM0;
42 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) ==
43 SYSMGR_FPGAINTF_USEFPGA)
44 handoff_val |= SYSMGR_FPGAINTF_SPIM1;
45 writel(handoff_val,
46 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2);
47
48 handoff_val = 0;
49 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) ==
50 SYSMGR_FPGAINTF_USEFPGA)
51 handoff_val |= SYSMGR_FPGAINTF_EMAC0;
52 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) ==
53 SYSMGR_FPGAINTF_USEFPGA)
54 handoff_val |= SYSMGR_FPGAINTF_EMAC1;
55 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) ==
56 SYSMGR_FPGAINTF_USEFPGA)
57 handoff_val |= SYSMGR_FPGAINTF_EMAC2;
58 writel(handoff_val,
59 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3);
60 }
61
62 /*
63 * Configure all the pin muxes
64 */
populate_sysmgr_pinmux(void)65 void populate_sysmgr_pinmux(void)
66 {
67 const u32 *sys_mgr_table_u32;
68 unsigned int len, i;
69
70 /* setup the pin sel */
71 sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
72 for (i = 0; i < len; i = i + 2) {
73 writel(sys_mgr_table_u32[i + 1],
74 sys_mgr_table_u32[i] +
75 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0);
76 }
77
78 /* setup the pin ctrl */
79 sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
80 for (i = 0; i < len; i = i + 2) {
81 writel(sys_mgr_table_u32[i + 1],
82 sys_mgr_table_u32[i] +
83 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0);
84 }
85
86 /* setup the fpga use */
87 sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
88 for (i = 0; i < len; i = i + 2) {
89 writel(sys_mgr_table_u32[i + 1],
90 sys_mgr_table_u32[i] +
91 (u8 *)socfpga_get_sysmgr_addr() +
92 SYSMGR_SOC64_EMAC0_USEFPGA);
93 }
94
95 /* setup the IO delay */
96 sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
97 for (i = 0; i < len; i = i + 2) {
98 writel(sys_mgr_table_u32[i + 1],
99 sys_mgr_table_u32[i] +
100 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0);
101 }
102 }
103