1 /*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <common/debug.h>
12 #include <plat/common/platform.h>
13
14 #include "psci_private.h"
15
16 #ifndef PLAT_MAX_PWR_LVL_STATES
17 #define PLAT_MAX_PWR_LVL_STATES 2U
18 #endif
19
20 /* Following structure is used for PSCI STAT */
21 typedef struct psci_stat {
22 u_register_t residency;
23 u_register_t count;
24 } psci_stat_t;
25
26 /*
27 * Following is used to keep track of the last cpu
28 * that goes to power down in non cpu power domains.
29 */
30 static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {
31 [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1U] = -1};
32
33 /*
34 * Following are used to store PSCI STAT values for
35 * CPU and non CPU power domains.
36 */
37 static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT]
38 [PLAT_MAX_PWR_LVL_STATES];
39 static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS]
40 [PLAT_MAX_PWR_LVL_STATES];
41
42 /*
43 * This functions returns the index into the `psci_stat_t` array given the
44 * local power state and power domain level. If the platform implements the
45 * `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index.
46 */
get_stat_idx(plat_local_state_t local_state,unsigned int pwr_lvl)47 static int get_stat_idx(plat_local_state_t local_state, unsigned int pwr_lvl)
48 {
49 int idx;
50
51 if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) {
52 assert(PLAT_MAX_PWR_LVL_STATES == 2U);
53 if (is_local_state_retn(local_state) != 0)
54 return 0;
55
56 assert(is_local_state_off(local_state) != 0);
57 return 1;
58 }
59
60 idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl);
61 assert((idx >= 0) && (idx < (int) PLAT_MAX_PWR_LVL_STATES));
62 return idx;
63 }
64
65 /*******************************************************************************
66 * This function is passed the target local power states for each power
67 * domain (state_info) between the current CPU domain and its ancestors until
68 * the target power level (end_pwrlvl).
69 *
70 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
71 * updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id.
72 *
73 * This function will only be invoked with data cache enabled and while
74 * powering down a core.
75 ******************************************************************************/
psci_stats_update_pwr_down(unsigned int end_pwrlvl,const psci_power_state_t * state_info)76 void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
77 const psci_power_state_t *state_info)
78 {
79 unsigned int lvl, parent_idx;
80 unsigned int cpu_idx = plat_my_core_pos();
81
82 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
83 assert(state_info != NULL);
84
85 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
86
87 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
88
89 /* Break early if the target power state is RUN */
90 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
91 break;
92
93 /*
94 * The power domain is entering a low power state, so this is
95 * the last CPU for this power domain
96 */
97 last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx;
98
99 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
100 }
101
102 }
103
104 /*******************************************************************************
105 * This function updates the PSCI STATS(residency time and count) for CPU
106 * and NON-CPU power domains.
107 * It is called with caches enabled and locks acquired(for NON-CPU domain)
108 ******************************************************************************/
psci_stats_update_pwr_up(unsigned int end_pwrlvl,const psci_power_state_t * state_info)109 void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
110 const psci_power_state_t *state_info)
111 {
112 unsigned int lvl, parent_idx;
113 unsigned int cpu_idx = plat_my_core_pos();
114 int stat_idx;
115 plat_local_state_t local_state;
116 u_register_t residency;
117
118 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
119 assert(state_info != NULL);
120
121 /* Get the index into the stats array */
122 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
123 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL);
124
125 /* Call into platform interface to calculate residency. */
126 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL,
127 state_info, cpu_idx);
128
129 /* Update CPU stats. */
130 psci_cpu_stat[cpu_idx][stat_idx].residency += residency;
131 psci_cpu_stat[cpu_idx][stat_idx].count++;
132
133 /*
134 * Check what power domains above CPU were off
135 * prior to this CPU powering on.
136 */
137 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
138 /* Return early if this is the first power up. */
139 if (last_cpu_in_non_cpu_pd[parent_idx] == -1)
140 return;
141
142 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
143 local_state = state_info->pwr_domain_state[lvl];
144 if (is_local_state_run(local_state) != 0) {
145 /* Break early */
146 break;
147 }
148
149 assert(last_cpu_in_non_cpu_pd[parent_idx] != -1);
150
151 /* Call into platform interface to calculate residency. */
152 residency = plat_psci_stat_get_residency(lvl, state_info,
153 (unsigned int)last_cpu_in_non_cpu_pd[parent_idx]);
154
155 /* Initialize back to reset value */
156 last_cpu_in_non_cpu_pd[parent_idx] = -1;
157
158 /* Get the index into the stats array */
159 stat_idx = get_stat_idx(local_state, lvl);
160
161 /* Update non cpu stats */
162 psci_non_cpu_stat[parent_idx][stat_idx].residency += residency;
163 psci_non_cpu_stat[parent_idx][stat_idx].count++;
164
165 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
166 }
167
168 }
169
170 /*******************************************************************************
171 * This function returns the appropriate count and residency time of the
172 * local state for the highest power level expressed in the `power_state`
173 * for the node represented by `target_cpu`.
174 ******************************************************************************/
psci_get_stat(u_register_t target_cpu,unsigned int power_state,psci_stat_t * psci_stat)175 static int psci_get_stat(u_register_t target_cpu, unsigned int power_state,
176 psci_stat_t *psci_stat)
177 {
178 int rc;
179 unsigned int pwrlvl, lvl, parent_idx, target_idx;
180 int stat_idx;
181 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
182 plat_local_state_t local_state;
183
184 /* Validate the target_cpu parameter and determine the cpu index */
185 target_idx = (unsigned int) plat_core_pos_by_mpidr(target_cpu);
186 if (target_idx == (unsigned int) -1)
187 return PSCI_E_INVALID_PARAMS;
188
189 /* Validate the power_state parameter */
190 if (psci_plat_pm_ops->translate_power_state_by_mpidr == NULL)
191 rc = psci_validate_power_state(power_state, &state_info);
192 else
193 rc = psci_plat_pm_ops->translate_power_state_by_mpidr(
194 target_cpu, power_state, &state_info);
195
196 if (rc != PSCI_E_SUCCESS)
197 return PSCI_E_INVALID_PARAMS;
198
199 /* Find the highest power level */
200 pwrlvl = psci_find_target_suspend_lvl(&state_info);
201 if (pwrlvl == PSCI_INVALID_PWR_LVL) {
202 ERROR("Invalid target power level for PSCI statistics operation\n");
203 panic();
204 }
205
206 /* Get the index into the stats array */
207 local_state = state_info.pwr_domain_state[pwrlvl];
208 stat_idx = get_stat_idx(local_state, pwrlvl);
209
210 if (pwrlvl > PSCI_CPU_PWR_LVL) {
211 /* Get the power domain index */
212 parent_idx = SPECULATION_SAFE_VALUE(psci_cpu_pd_nodes[target_idx].parent_node);
213 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++)
214 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node);
215
216 /* Get the non cpu power domain stats */
217 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
218 } else {
219 /* Get the cpu power domain stats */
220 *psci_stat = psci_cpu_stat[target_idx][stat_idx];
221 }
222
223 return PSCI_E_SUCCESS;
224 }
225
226 /* This is the top level function for PSCI_STAT_RESIDENCY SMC. */
psci_stat_residency(u_register_t target_cpu,unsigned int power_state)227 u_register_t psci_stat_residency(u_register_t target_cpu,
228 unsigned int power_state)
229 {
230 psci_stat_t psci_stat;
231 int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
232
233 if (rc == PSCI_E_SUCCESS)
234 return psci_stat.residency;
235 else
236 return 0;
237 }
238
239 /* This is the top level function for PSCI_STAT_COUNT SMC. */
psci_stat_count(u_register_t target_cpu,unsigned int power_state)240 u_register_t psci_stat_count(u_register_t target_cpu,
241 unsigned int power_state)
242 {
243 psci_stat_t psci_stat;
244 int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
245
246 if (rc == PSCI_E_SUCCESS)
247 return psci_stat.count;
248 else
249 return 0;
250 }
251