1 /*
2 * Copyright 2018-2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef CAAM_IO_H
9 #define CAAM_IO_H
10
11 #include <endian.h>
12 #include <lib/mmio.h>
13
14 typedef unsigned long long phys_addr_t;
15 typedef unsigned long long phys_size_t;
16
17 /* Return higher 32 bits of physical address */
18 #define PHYS_ADDR_HI(phys_addr) \
19 (uint32_t)(((uint64_t)phys_addr) >> 32)
20
21 /* Return lower 32 bits of physical address */
22 #define PHYS_ADDR_LO(phys_addr) \
23 (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF)
24
25 #ifdef NXP_SEC_BE
26 #define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
27 #define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
28 #define sec_in64(addr) ( \
29 ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
30 (sec_in32(((uintptr_t)(addr)) + 4)))
31 #define sec_out64(addr, val) ({ \
32 sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
33 sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
34 #elif defined(NXP_SEC_LE)
35 #define sec_in32(a) mmio_read_32((uintptr_t)(a))
36 #define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
37 #define sec_in64(addr) ( \
38 ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
39 (sec_in32((uintptr_t)(addr))))
40 #define sec_out64(addr, val) ({ \
41 sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \
42 sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); })
43 #else
44 #error Please define CCSR SEC register endianness
45 #endif
46
ptov(phys_addr_t * ptr)47 static inline void *ptov(phys_addr_t *ptr)
48 {
49 return (void *)ptr;
50 }
51
vtop(void * ptr)52 static inline phys_addr_t *vtop(void *ptr)
53 {
54 return (phys_addr_t *)ptr;
55 }
56 #endif /* CAAM_IO_H */
57