1 /*
2 * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10
11 #include "../qos_common.h"
12 #include "../qos_reg.h"
13 #include "qos_init_m3n_v10.h"
14
15 #define RCAR_QOS_VERSION "rev.0.09"
16
17 #define REF_ARS_ARBSTOPCYCLE_M3N \
18 (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
19
20 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */
21
22 #define QOSWT_WTEN_ENABLE 0x1U
23
24 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
25 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
26 #define QOSWT_WTREF_SLOT0_EN \
27 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
28 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
29 #define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
30
31 #define QOSWT_WTSET0_REQ_SSLOT0 5U
32 #define WT_BASE_SUB_SLOT_NUM0 12U
33 #define QOSWT_WTSET0_PERIOD0_M3N \
34 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3N) - 1U)
35 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
36 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
37
38 #define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
39 #define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
40 #define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
41
42 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
43
44 #if RCAR_REF_INT == RCAR_REF_DEFAULT
45 #include "qos_init_m3n_v10_mstat195.h"
46 #else
47 #include "qos_init_m3n_v10_mstat390.h"
48 #endif
49
50 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
51
52 #if RCAR_REF_INT == RCAR_REF_DEFAULT
53 #include "qos_init_m3n_v10_qoswt195.h"
54 #else
55 #include "qos_init_m3n_v10_qoswt390.h"
56 #endif
57
58 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
59 #endif
60
61 struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
62 /* BUFCAM settings */
63 { DBSC_DBCAM0CNF1, 0x00043218 },
64 { DBSC_DBCAM0CNF2, 0x000000F4 },
65 { DBSC_DBSCHCNT0, 0x000F0037 },
66 { DBSC_DBSCHSZ0, 0x00000001 },
67 { DBSC_DBSCHRW0, 0x22421111 },
68
69 /* DDR3 */
70 { DBSC_SCFCTST2, 0x012F1123 },
71
72 /* QoS Settings */
73 { DBSC_DBSCHQOS00, 0x00000F00 },
74 { DBSC_DBSCHQOS01, 0x00000B00 },
75 { DBSC_DBSCHQOS02, 0x00000000 },
76 { DBSC_DBSCHQOS03, 0x00000000 },
77 { DBSC_DBSCHQOS40, 0x00000300 },
78 { DBSC_DBSCHQOS41, 0x000002F0 },
79 { DBSC_DBSCHQOS42, 0x00000200 },
80 { DBSC_DBSCHQOS43, 0x00000100 },
81 { DBSC_DBSCHQOS90, 0x00000100 },
82 { DBSC_DBSCHQOS91, 0x000000F0 },
83 { DBSC_DBSCHQOS92, 0x000000A0 },
84 { DBSC_DBSCHQOS93, 0x00000040 },
85 { DBSC_DBSCHQOS130, 0x00000100 },
86 { DBSC_DBSCHQOS131, 0x000000F0 },
87 { DBSC_DBSCHQOS132, 0x000000A0 },
88 { DBSC_DBSCHQOS133, 0x00000040 },
89 { DBSC_DBSCHQOS140, 0x000000C0 },
90 { DBSC_DBSCHQOS141, 0x000000B0 },
91 { DBSC_DBSCHQOS142, 0x00000080 },
92 { DBSC_DBSCHQOS143, 0x00000040 },
93 { DBSC_DBSCHQOS150, 0x00000040 },
94 { DBSC_DBSCHQOS151, 0x00000030 },
95 { DBSC_DBSCHQOS152, 0x00000020 },
96 { DBSC_DBSCHQOS153, 0x00000010 },
97 };
98
qos_init_m3n_v10(void)99 void qos_init_m3n_v10(void)
100 {
101 rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true);
102
103 /* DRAM Split Address mapping */
104 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
105 #if RCAR_LSI == RCAR_M3N
106 #error "Don't set DRAM Split 4ch(M3N)"
107 #else
108 ERROR("DRAM Split 4ch not supported.(M3N)");
109 panic();
110 #endif
111 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
112 #if RCAR_LSI == RCAR_M3N
113 #error "Don't set DRAM Split 2ch(M3N)"
114 #else
115 ERROR("DRAM Split 2ch not supported.(M3N)");
116 panic();
117 #endif
118 #else
119 NOTICE("BL2: DRAM Split is OFF\n");
120 #endif
121
122 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
123 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
124 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
125 #endif
126
127 #if RCAR_REF_INT == RCAR_REF_DEFAULT
128 NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
129 #else
130 NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
131 #endif
132
133 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
134 NOTICE("BL2: Periodic Write DQ Training\n");
135 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
136
137 io_write_32(QOSCTRL_RAS, 0x00000028U);
138 io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
139 io_write_32(QOSCTRL_DANT, 0x00100804U);
140 io_write_32(QOSCTRL_FSS, 0x0000000AU);
141 io_write_32(QOSCTRL_INSFC, 0x06330001U);
142 io_write_32(QOSCTRL_EARLYR, 0x00000001U);
143 io_write_32(QOSCTRL_RACNT0, 0x00010003U);
144
145 io_write_32(QOSCTRL_SL_INIT,
146 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
147 SL_INIT_SSLOTCLK_M3N);
148 io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
149
150 uint32_t i;
151
152 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
153 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
154 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
155 }
156 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
157 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
158 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
159 }
160 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
161 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
162 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
163 qoswt_fix[i]);
164 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
165 qoswt_fix[i]);
166 }
167 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
168 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
169 io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
170 }
171 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
172
173 /* RT bus Leaf setting */
174 io_write_32(RT_ACT0, 0x00000000U);
175 io_write_32(RT_ACT1, 0x00000000U);
176
177 /* CCI bus Leaf setting */
178 io_write_32(CPU_ACT0, 0x00000003U);
179 io_write_32(CPU_ACT1, 0x00000003U);
180
181 io_write_32(QOSCTRL_RAEN, 0x00000001U);
182
183 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
184 /* re-write training setting */
185 io_write_32(QOSWT_WTREF,
186 ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
187 io_write_32(QOSWT_WTSET0,
188 ((QOSWT_WTSET0_PERIOD0_M3N << 16) |
189 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
190 io_write_32(QOSWT_WTSET1,
191 ((QOSWT_WTSET1_PERIOD1_M3N << 16) |
192 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
193
194 io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
195 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
196
197 io_write_32(QOSCTRL_STATQC, 0x00000001U);
198 #else
199 NOTICE("BL2: QoS is None\n");
200
201 io_write_32(QOSCTRL_RAEN, 0x00000001U);
202 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
203 }
204