1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <linux/bitops.h>
10
11 #include "common.h"
12 #include "qrio.h"
13
14 /* QRIO ID register offset */
15 #define ID_REV_OFF 0x00
16
17 /* QRIO GPIO register offsets */
18 #define DIRECT_OFF 0x18
19 #define GPRT_OFF 0x1c
20
show_qrio(void)21 void show_qrio(void)
22 {
23 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
24 u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
25
26 printf("QRIO: id = %u, revision = %u\n",
27 (id_rev >> 8) & 0xff, id_rev & 0xff);
28 }
29
qrio_get_gpio(u8 port_off,u8 gpio_nr)30 int qrio_get_gpio(u8 port_off, u8 gpio_nr)
31 {
32 u32 gprt;
33
34 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
35
36 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
37
38 return (gprt >> gpio_nr) & 1U;
39 }
40
qrio_set_gpio(u8 port_off,u8 gpio_nr,bool value)41 void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
42 {
43 u32 gprt, mask;
44
45 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
46
47 mask = 1U << gpio_nr;
48
49 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
50 if (value)
51 gprt |= mask;
52 else
53 gprt &= ~mask;
54
55 out_be32(qrio_base + port_off + GPRT_OFF, gprt);
56 }
57
qrio_gpio_direction_output(u8 port_off,u8 gpio_nr,bool value)58 void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
59 {
60 u32 direct, mask;
61
62 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
63
64 mask = 1U << gpio_nr;
65
66 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
67 direct |= mask;
68 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
69
70 qrio_set_gpio(port_off, gpio_nr, value);
71 }
72
qrio_gpio_direction_input(u8 port_off,u8 gpio_nr)73 void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
74 {
75 u32 direct, mask;
76
77 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
78
79 mask = 1U << gpio_nr;
80
81 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
82 direct &= ~mask;
83 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
84 }
85
qrio_set_opendrain_gpio(u8 port_off,u8 gpio_nr,u8 val)86 void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
87 {
88 u32 direct, mask;
89
90 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
91
92 mask = 1U << gpio_nr;
93
94 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
95 if (val == 0)
96 /* set to output -> GPIO drives low */
97 direct |= mask;
98 else
99 /* set to input -> GPIO floating */
100 direct &= ~mask;
101
102 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
103 }
104
105 #define WDMASK_OFF 0x16
106
qrio_wdmask(u8 bit,bool wden)107 void qrio_wdmask(u8 bit, bool wden)
108 {
109 u16 wdmask;
110 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
111
112 wdmask = in_be16(qrio_base + WDMASK_OFF);
113
114 if (wden)
115 wdmask |= (1 << bit);
116 else
117 wdmask &= ~(1 << bit);
118
119 out_be16(qrio_base + WDMASK_OFF, wdmask);
120 }
121
122 #define PRST_OFF 0x1a
123
qrio_prst(u8 bit,bool en,bool wden)124 void qrio_prst(u8 bit, bool en, bool wden)
125 {
126 u16 prst;
127 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
128
129 qrio_wdmask(bit, wden);
130
131 prst = in_be16(qrio_base + PRST_OFF);
132
133 if (en)
134 prst &= ~(1 << bit);
135 else
136 prst |= (1 << bit);
137
138 out_be16(qrio_base + PRST_OFF, prst);
139 }
140
141 #define PRSTCFG_OFF 0x1c
142
qrio_prstcfg(u8 bit,u8 mode)143 void qrio_prstcfg(u8 bit, u8 mode)
144 {
145 unsigned long prstcfg;
146 u8 i;
147 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
148
149 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
150
151 for (i = 0; i < 2; i++) {
152 if (mode & (1 << i))
153 __set_bit(2 * bit + i, &prstcfg);
154 else
155 __clear_bit(2 * bit + i, &prstcfg);
156 }
157
158 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
159 }
160
161 #define CTRLH_OFF 0x02
162 #define CTRLH_WRL_BOOT 0x01
163 #define CTRLH_WRL_UNITRUN 0x02
164
qrio_set_leds(void)165 void qrio_set_leds(void)
166 {
167 u8 ctrlh;
168 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
169
170 /* set UNIT LED to RED and BOOT LED to ON */
171 ctrlh = in_8(qrio_base + CTRLH_OFF);
172 ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
173 out_8(qrio_base + CTRLH_OFF, ctrlh);
174 }
175
176 #define CTRLL_OFF 0x03
177 #define CTRLL_WRB_BUFENA 0x20
178
qrio_enable_app_buffer(void)179 void qrio_enable_app_buffer(void)
180 {
181 u8 ctrll;
182 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
183
184 /* enable application buffer */
185 ctrll = in_8(qrio_base + CTRLL_OFF);
186 ctrll |= (CTRLL_WRB_BUFENA);
187 out_8(qrio_base + CTRLL_OFF, ctrll);
188 }
189
190 #define REASON1_OFF 0x12
191 #define REASON1_CPUWD 0x01
192
qrio_cpuwd_flag(bool flag)193 void qrio_cpuwd_flag(bool flag)
194 {
195 u8 reason1;
196 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
197
198 reason1 = in_8(qrio_base + REASON1_OFF);
199 if (flag)
200 reason1 |= REASON1_CPUWD;
201 else
202 reason1 &= ~REASON1_CPUWD;
203 out_8(qrio_base + REASON1_OFF, reason1);
204 }
205
206 #define REASON0_OFF 0x13
207 #define REASON0_SWURST 0x80
208 #define REASON0_CPURST 0x40
209 #define REASON0_BPRST 0x20
210 #define REASON0_COPRST 0x10
211 #define REASON0_SWCRST 0x08
212 #define REASON0_WDRST 0x04
213 #define REASON0_KBRST 0x02
214 #define REASON0_POWUP 0x01
215 #define UNIT_RESET\
216 (REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\
217 REASON0_BPRST | REASON0_SWURST | REASON0_WDRST)
218 #define CORE_RESET ((REASON1_CPUWD << 8) | REASON0_SWCRST)
219
qrio_reason_unitrst(void)220 bool qrio_reason_unitrst(void)
221 {
222 u16 reason;
223 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
224
225 reason = in_be16(qrio_base + REASON1_OFF);
226
227 return (reason & UNIT_RESET) > 0;
228 }
229
230 #define RSTCFG_OFF 0x11
231
qrio_uprstreq(u8 mode)232 void qrio_uprstreq(u8 mode)
233 {
234 u32 rstcfg;
235 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
236
237 rstcfg = in_8(qrio_base + RSTCFG_OFF);
238
239 if (mode & UPREQ_CORE_RST)
240 rstcfg |= UPREQ_CORE_RST;
241 else
242 rstcfg &= ~UPREQ_CORE_RST;
243
244 out_8(qrio_base + RSTCFG_OFF, rstcfg);
245 }
246
247 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
248 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
249 * For I2C only the low state is activly driven and high state is pulled-up
250 * by a resistor. Therefore the deblock GPIOs are used
251 * -> as an active output to drive a low state
252 * -> as an open-drain input to have a pulled-up high state
253 */
254
255 /* By default deblock GPIOs are floating */
i2c_deblock_gpio_cfg(void)256 void i2c_deblock_gpio_cfg(void)
257 {
258 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
259 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
260 KM_I2C_DEBLOCK_SCL);
261 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
262 KM_I2C_DEBLOCK_SDA);
263
264 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
265 KM_I2C_DEBLOCK_SCL, 0);
266 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
267 KM_I2C_DEBLOCK_SDA, 0);
268 }
269
set_sda(int state)270 void set_sda(int state)
271 {
272 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
273 KM_I2C_DEBLOCK_SDA, state);
274 }
275
set_scl(int state)276 void set_scl(int state)
277 {
278 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
279 KM_I2C_DEBLOCK_SCL, state);
280 }
281
get_sda(void)282 int get_sda(void)
283 {
284 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
285 KM_I2C_DEBLOCK_SDA);
286 }
287
get_scl(void)288 int get_scl(void)
289 {
290 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
291 KM_I2C_DEBLOCK_SCL);
292 }
293
294