1 /*
2  * Copyright (C) 2021  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef __AMDGPU_MCA_H__
22 #define __AMDGPU_MCA_H__
23 
24 struct amdgpu_mca_ras_funcs {
25 	int (*ras_late_init)(struct amdgpu_device *adev);
26 	void (*ras_fini)(struct amdgpu_device *adev);
27 	void (*query_ras_error_count)(struct amdgpu_device *adev,
28 				      void *ras_error_status);
29 	void (*query_ras_error_address)(struct amdgpu_device *adev,
30 					void *ras_error_status);
31 	uint32_t ras_block;
32 	uint32_t ras_sub_block;
33 	const char* sysfs_name;
34 };
35 
36 struct amdgpu_mca_ras {
37 	struct ras_common_if *ras_if;
38 	const struct amdgpu_mca_ras_funcs *ras_funcs;
39 };
40 
41 struct amdgpu_mca_funcs {
42 	void (*init)(struct amdgpu_device *adev);
43 };
44 
45 struct amdgpu_mca {
46 	const struct amdgpu_mca_funcs *funcs;
47 	struct amdgpu_mca_ras mp0;
48 	struct amdgpu_mca_ras mp1;
49 	struct amdgpu_mca_ras mpio;
50 };
51 
52 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
53 					      uint64_t mc_status_addr,
54 					      unsigned long *error_count);
55 
56 void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
57 						uint64_t mc_status_addr,
58 						unsigned long *error_count);
59 
60 void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
61 				  uint64_t mc_status_addr);
62 
63 void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
64 				      uint64_t mc_status_addr,
65 				      void *ras_error_status);
66 
67 int amdgpu_mca_ras_late_init(struct amdgpu_device *adev,
68 			     struct amdgpu_mca_ras *mca_dev);
69 
70 void amdgpu_mca_ras_fini(struct amdgpu_device *adev,
71 			 struct amdgpu_mca_ras *mca_dev);
72 
73 #endif
74