| /tf-a-ffa_el3_spmc/drivers/renesas/rcar/pfc/ |
| A D | pfc_init.c | 40 #define PRR_PRODUCT_ERR(reg) \ argument
47 #define PRR_CUT_ERR(reg) \ argument
56 uint32_t reg; in rcar_pfc_init() local
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| /tf-a-ffa_el3_spmc/drivers/renesas/rzg/pfc/ |
| A D | pfc_init.c | 31 #define PRR_PRODUCT_ERR(reg) \ argument
38 #define PRR_CUT_ERR(reg) \ argument
47 uint32_t reg; in rzg_pfc_init() local
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| /tf-a-ffa_el3_spmc/drivers/renesas/rcar/qos/ |
| A D | qos_init.c | 61 #define PRR_PRODUCT_ERR(reg) \ argument
68 #define PRR_CUT_ERR(reg) \ argument
77 uint32_t reg; in rcar_qos_init() local
300 uint32_t reg; in get_refperiod() local
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| /tf-a-ffa_el3_spmc/drivers/renesas/rzg/qos/ |
| A D | qos_init.c | 45 #define PRR_PRODUCT_ERR(reg) \ argument
52 #define PRR_CUT_ERR(reg) \ argument
61 uint32_t reg; in rzg_qos_init() local
196 uint32_t reg; in get_refperiod() local
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| /tf-a-ffa_el3_spmc/plat/imx/common/sci/ |
| A D | imx8_mu.c | 13 uint32_t reg, i; in MU_Resume() local
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt() local
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt() local
66 uint32_t reg; in MU_Init() local
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| /tf-a-ffa_el3_spmc/drivers/brcm/mdio/ |
| A D | mdio.c | 31 static int mdio_op(uint16_t busid, uint16_t phyid, uint32_t reg, in mdio_op()
67 int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val) in mdio_write()
78 int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg) in mdio_read()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spmc/ |
| A D | mtspmc.c | 42 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_enable_cpu_auto_off() local
50 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_disable_cpu_auto_off() local
75 uintptr_t reg; in mcucfg_set_bootaddr() local
92 uintptr_t reg; in mcucfg_get_bootaddr() local
109 uintptr_t reg; in mcucfg_init_archstate() local
|
| /tf-a-ffa_el3_spmc/plat/intel/soc/common/drivers/ccu/ |
| A D | ncore_ccu.h | 70 #define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ argument
72 #define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ argument
74 #define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ argument
77 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ argument
79 #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ argument
82 #define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ argument
|
| /tf-a-ffa_el3_spmc/drivers/renesas/rcar/cpld/ |
| A D | ulcb_cpld.c | 36 uint32_t reg; in gpio_set_value() local
48 uint32_t reg; in gpio_direction_output() local
57 uint32_t reg; in gpio_pfc() local
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| /tf-a-ffa_el3_spmc/plat/renesas/common/ |
| A D | bl2_secure_setting.c | 18 uint32_t reg; member
263 uint32_t reg; member
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey/ |
| A D | hisi_pwrc.c | 42 unsigned int reg = 0; in hisi_pwrc_set_cluster_wfi() local
72 unsigned int reg, sec_entrypoint; in hisi_pwrc_setup() local
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| /tf-a-ffa_el3_spmc/drivers/allwinner/axp/ |
| A D | common.c | 31 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) in axp_clrsetbits()
77 const struct axp_regulator *reg) in setup_regulator()
174 const struct axp_regulator *reg; in axp_setup_regulators() local
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| /tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h6/ |
| A D | sunxi_power.c | 28 int axp_read(uint8_t reg) in axp_read()
33 int axp_write(uint8_t reg, uint8_t val) in axp_write()
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/bpmp_ipc/ |
| A D | intf.c | 38 static inline uint32_t hsp_db_read(uint32_t reg) in hsp_db_read()
43 static inline void hsp_db_write(uint32_t reg, uint32_t val) in hsp_db_write()
108 uint32_t reg; in tegra_bpmp_enable_ccplex_doorbell() local
134 uint32_t reg; in tegra_bpmp_can_ccplex_ring_doorbell() local
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| /tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h616/ |
| A D | sunxi_power.c | 31 int axp_read(uint8_t reg) in axp_read()
36 int axp_write(uint8_t reg, uint8_t val) in axp_write()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/timer/ |
| A D | mt_timer.c | 15 unsigned int reg; in enable_systimer_compensation() local
|
| /tf-a-ffa_el3_spmc/plat/imx/common/ |
| A D | imx_caam.c | 16 uint32_t reg; in imx_caam_init() local
|
| /tf-a-ffa_el3_spmc/drivers/allwinner/ |
| A D | sunxi_rsb.c | 39 uint32_t reg, tries = MAX_TRIES; in rsb_wait_bit() local
54 uint32_t reg; in rsb_wait_stat() local
113 uint32_t reg; in rsb_set_bus_speed() local
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| /tf-a-ffa_el3_spmc/drivers/nxp/dcfg/ |
| A D | dcfg.c | 38 uint32_t reg; in get_soc_info() local
70 uint32_t reg; in get_devdisr5_info() local
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| /tf-a-ffa_el3_spmc/include/drivers/allwinner/ |
| A D | axp.h | 45 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) argument
46 #define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) argument
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| /tf-a-ffa_el3_spmc/drivers/nxp/csu/ |
| A D | csu.c | 18 uint32_t *reg; in enable_layerscape_ns_access() local
|
| /tf-a-ffa_el3_spmc/plat/allwinner/sun50i_a64/ |
| A D | sunxi_power.c | 115 int axp_read(uint8_t reg) in axp_read()
120 int axp_write(uint8_t reg, uint8_t val) in axp_write()
|
| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/ |
| A D | plat_thermal.c | 45 uint32_t reg, timeout = 0; in ext_tsen_probe() local
85 uint32_t reg; in ext_tsen_read() local
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| /tf-a-ffa_el3_spmc/drivers/renesas/common/ |
| A D | common.c | 31 uint32_t reg; in mstpcr_write() local
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| /tf-a-ffa_el3_spmc/plat/layerscape/common/ |
| A D | ns_access.c | 19 uint32_t *reg; in enable_devices_ns_access() local
|