1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_FW_NAME_LEN 0x24 40 41 enum psp_shared_mem_size { 42 PSP_ASD_SHARED_MEM_SIZE = 0x0, 43 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 44 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 45 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 46 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 48 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 49 }; 50 51 struct psp_context; 52 struct psp_xgmi_node_info; 53 struct psp_xgmi_topology_info; 54 struct psp_bin_desc; 55 56 enum psp_bootloader_cmd { 57 PSP_BL__LOAD_SYSDRV = 0x10000, 58 PSP_BL__LOAD_SOSDRV = 0x20000, 59 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 60 PSP_BL__LOAD_SOCDRV = 0xB0000, 61 PSP_BL__LOAD_INTFDRV = 0xC0000, 62 PSP_BL__LOAD_DBGDRV = 0xD0000, 63 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 64 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 65 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 66 }; 67 68 enum psp_ring_type 69 { 70 PSP_RING_TYPE__INVALID = 0, 71 /* 72 * These values map to the way the PSP kernel identifies the 73 * rings. 74 */ 75 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 76 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 77 }; 78 79 struct psp_ring 80 { 81 enum psp_ring_type ring_type; 82 struct psp_gfx_rb_frame *ring_mem; 83 uint64_t ring_mem_mc_addr; 84 void *ring_mem_handle; 85 uint32_t ring_size; 86 uint32_t ring_wptr; 87 }; 88 89 /* More registers may will be supported */ 90 enum psp_reg_prog_id { 91 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 92 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 93 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 94 PSP_REG_LAST 95 }; 96 97 struct psp_funcs 98 { 99 int (*init_microcode)(struct psp_context *psp); 100 int (*bootloader_load_kdb)(struct psp_context *psp); 101 int (*bootloader_load_spl)(struct psp_context *psp); 102 int (*bootloader_load_sysdrv)(struct psp_context *psp); 103 int (*bootloader_load_soc_drv)(struct psp_context *psp); 104 int (*bootloader_load_intf_drv)(struct psp_context *psp); 105 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 106 int (*bootloader_load_sos)(struct psp_context *psp); 107 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 108 int (*ring_create)(struct psp_context *psp, 109 enum psp_ring_type ring_type); 110 int (*ring_stop)(struct psp_context *psp, 111 enum psp_ring_type ring_type); 112 int (*ring_destroy)(struct psp_context *psp, 113 enum psp_ring_type ring_type); 114 bool (*smu_reload_quirk)(struct psp_context *psp); 115 int (*mode1_reset)(struct psp_context *psp); 116 int (*mem_training)(struct psp_context *psp, uint32_t ops); 117 uint32_t (*ring_get_wptr)(struct psp_context *psp); 118 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 119 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 120 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 121 }; 122 123 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 124 struct psp_xgmi_node_info { 125 uint64_t node_id; 126 uint8_t num_hops; 127 uint8_t is_sharing_enabled; 128 enum ta_xgmi_assigned_sdma_engine sdma_engine; 129 uint8_t num_links; 130 }; 131 132 struct psp_xgmi_topology_info { 133 uint32_t num_nodes; 134 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 135 }; 136 137 struct psp_bin_desc { 138 uint32_t fw_version; 139 uint32_t feature_version; 140 uint32_t size_bytes; 141 uint8_t *start_addr; 142 }; 143 144 struct ta_mem_context { 145 struct amdgpu_bo *shared_bo; 146 uint64_t shared_mc_addr; 147 void *shared_buf; 148 enum psp_shared_mem_size shared_mem_size; 149 }; 150 151 struct ta_context { 152 bool initialized; 153 uint32_t session_id; 154 struct ta_mem_context mem_context; 155 struct psp_bin_desc bin_desc; 156 enum psp_gfx_cmd_id ta_load_type; 157 }; 158 159 struct ta_cp_context { 160 struct ta_context context; 161 struct mutex mutex; 162 }; 163 164 struct psp_xgmi_context { 165 struct ta_context context; 166 struct psp_xgmi_topology_info top_info; 167 bool supports_extended_data; 168 }; 169 170 struct psp_ras_context { 171 struct ta_context context; 172 struct amdgpu_ras *ras; 173 }; 174 175 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 176 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 177 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 178 /*Define the VRAM size that will be encroached by BIST training.*/ 179 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 180 181 enum psp_memory_training_init_flag { 182 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 183 PSP_MEM_TRAIN_SUPPORT = 0x1, 184 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 185 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 186 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 187 }; 188 189 enum psp_memory_training_ops { 190 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 191 PSP_MEM_TRAIN_SAVE = 0x2, 192 PSP_MEM_TRAIN_RESTORE = 0x4, 193 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 194 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 195 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 196 }; 197 198 struct psp_memory_training_context { 199 /*training data size*/ 200 u64 train_data_size; 201 /* 202 * sys_cache 203 * cpu virtual address 204 * system memory buffer that used to store the training data. 205 */ 206 void *sys_cache; 207 208 /*vram offset of the p2c training data*/ 209 u64 p2c_train_data_offset; 210 211 /*vram offset of the c2p training data*/ 212 u64 c2p_train_data_offset; 213 struct amdgpu_bo *c2p_bo; 214 215 enum psp_memory_training_init_flag init; 216 u32 training_cnt; 217 bool enable_mem_training; 218 }; 219 220 /** PSP runtime DB **/ 221 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 222 #define PSP_RUNTIME_DB_OFFSET 0x100000 223 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 224 #define PSP_RUNTIME_DB_VER_1 0x0100 225 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 226 227 enum psp_runtime_entry_type { 228 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 229 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 230 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 231 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 232 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 233 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 234 }; 235 236 /* PSP runtime DB header */ 237 struct psp_runtime_data_header { 238 /* determine the existence of runtime db */ 239 uint16_t cookie; 240 /* version of runtime db */ 241 uint16_t version; 242 }; 243 244 /* PSP runtime DB entry */ 245 struct psp_runtime_entry { 246 /* type of runtime db entry */ 247 uint32_t entry_type; 248 /* offset of entry in bytes */ 249 uint16_t offset; 250 /* size of entry in bytes */ 251 uint16_t size; 252 }; 253 254 /* PSP runtime DB directory */ 255 struct psp_runtime_data_directory { 256 /* number of valid entries */ 257 uint16_t entry_count; 258 /* db entries*/ 259 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 260 }; 261 262 /* PSP runtime DB boot config feature bitmask */ 263 enum psp_runtime_boot_cfg_feature { 264 BOOT_CFG_FEATURE_GECC = 0x1, 265 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 266 }; 267 268 /* PSP runtime DB boot config entry */ 269 struct psp_runtime_boot_cfg_entry { 270 uint32_t boot_cfg_bitmask; 271 uint32_t reserved; 272 }; 273 274 struct psp_context 275 { 276 struct amdgpu_device *adev; 277 struct psp_ring km_ring; 278 struct psp_gfx_cmd_resp *cmd; 279 280 const struct psp_funcs *funcs; 281 282 /* firmware buffer */ 283 struct amdgpu_bo *fw_pri_bo; 284 uint64_t fw_pri_mc_addr; 285 void *fw_pri_buf; 286 287 /* sos firmware */ 288 const struct firmware *sos_fw; 289 struct psp_bin_desc sys; 290 struct psp_bin_desc sos; 291 struct psp_bin_desc toc; 292 struct psp_bin_desc kdb; 293 struct psp_bin_desc spl; 294 struct psp_bin_desc rl; 295 struct psp_bin_desc soc_drv; 296 struct psp_bin_desc intf_drv; 297 struct psp_bin_desc dbg_drv; 298 299 /* tmr buffer */ 300 struct amdgpu_bo *tmr_bo; 301 uint64_t tmr_mc_addr; 302 303 /* asd firmware */ 304 const struct firmware *asd_fw; 305 306 /* toc firmware */ 307 const struct firmware *toc_fw; 308 309 /* fence buffer */ 310 struct amdgpu_bo *fence_buf_bo; 311 uint64_t fence_buf_mc_addr; 312 void *fence_buf; 313 314 /* cmd buffer */ 315 struct amdgpu_bo *cmd_buf_bo; 316 uint64_t cmd_buf_mc_addr; 317 struct psp_gfx_cmd_resp *cmd_buf_mem; 318 319 /* fence value associated with cmd buffer */ 320 atomic_t fence_value; 321 /* flag to mark whether gfx fw autoload is supported or not */ 322 bool autoload_supported; 323 /* flag to mark whether df cstate management centralized to PMFW */ 324 bool pmfw_centralized_cstate_management; 325 326 /* xgmi ta firmware and buffer */ 327 const struct firmware *ta_fw; 328 uint32_t ta_fw_version; 329 330 struct ta_context asd_context; 331 struct psp_xgmi_context xgmi_context; 332 struct psp_ras_context ras_context; 333 struct ta_cp_context hdcp_context; 334 struct ta_cp_context dtm_context; 335 struct ta_cp_context rap_context; 336 struct ta_cp_context securedisplay_context; 337 struct mutex mutex; 338 struct psp_memory_training_context mem_train_ctx; 339 340 uint32_t boot_cfg_bitmask; 341 }; 342 343 struct amdgpu_psp_funcs { 344 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 345 enum AMDGPU_UCODE_ID); 346 }; 347 348 349 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 350 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 351 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 352 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 353 #define psp_init_microcode(psp) \ 354 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 355 #define psp_bootloader_load_kdb(psp) \ 356 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 357 #define psp_bootloader_load_spl(psp) \ 358 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 359 #define psp_bootloader_load_sysdrv(psp) \ 360 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 361 #define psp_bootloader_load_soc_drv(psp) \ 362 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 363 #define psp_bootloader_load_intf_drv(psp) \ 364 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 365 #define psp_bootloader_load_dbg_drv(psp) \ 366 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 367 #define psp_bootloader_load_sos(psp) \ 368 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 369 #define psp_smu_reload_quirk(psp) \ 370 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 371 #define psp_mode1_reset(psp) \ 372 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 373 #define psp_mem_training(psp, ops) \ 374 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 375 376 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 377 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 378 379 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 380 ((psp)->funcs->load_usbc_pd_fw ? \ 381 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 382 383 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 384 ((psp)->funcs->read_usbc_pd_fw ? \ 385 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 386 387 extern const struct amd_ip_funcs psp_ip_funcs; 388 389 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 390 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 391 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 392 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 393 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 394 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 395 396 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 397 uint32_t field_val, uint32_t mask, bool check_changed); 398 399 int psp_gpu_reset(struct amdgpu_device *adev); 400 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 401 uint64_t cmd_gpu_addr, int cmd_size); 402 403 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 404 int psp_xgmi_terminate(struct psp_context *psp); 405 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 406 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 407 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 408 int psp_xgmi_get_topology_info(struct psp_context *psp, 409 int number_devices, 410 struct psp_xgmi_topology_info *topology, 411 bool get_extended_data); 412 int psp_xgmi_set_topology_info(struct psp_context *psp, 413 int number_devices, 414 struct psp_xgmi_topology_info *topology); 415 416 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 417 int psp_ras_enable_features(struct psp_context *psp, 418 union ta_ras_cmd_input *info, bool enable); 419 int psp_ras_trigger_error(struct psp_context *psp, 420 struct ta_ras_trigger_error_input *info); 421 422 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 423 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 424 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 425 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 426 427 int psp_rlc_autoload_start(struct psp_context *psp); 428 429 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 430 uint32_t value); 431 int psp_ring_cmd_submit(struct psp_context *psp, 432 uint64_t cmd_buf_mc_addr, 433 uint64_t fence_mc_addr, 434 int index); 435 int psp_init_asd_microcode(struct psp_context *psp, 436 const char *chip_name); 437 int psp_init_toc_microcode(struct psp_context *psp, 438 const char *chip_name); 439 int psp_init_sos_microcode(struct psp_context *psp, 440 const char *chip_name); 441 int psp_init_ta_microcode(struct psp_context *psp, 442 const char *chip_name); 443 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 444 uint64_t *output_ptr); 445 446 int psp_load_fw_list(struct psp_context *psp, 447 struct amdgpu_firmware_info **ucode_list, int ucode_count); 448 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 449 450 int is_psp_fw_valid(struct psp_bin_desc bin); 451 #endif 452