1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
4 */
5 #include <common.h>
6 #include <bitfield.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/hardware.h>
14 #include <div64.h>
15 #include <linux/delay.h>
16
17 static struct rockchip_pll_rate_table rockchip_auto_table;
18
19 #define PLL_MODE_MASK 0x3
20 #define PLL_RK3328_MODE_MASK 0x1
21
22 #define RK3036_PLLCON0_FBDIV_MASK 0xfff
23 #define RK3036_PLLCON0_FBDIV_SHIFT 0
24 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12
25 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12
26 #define RK3036_PLLCON1_REFDIV_MASK 0x3f
27 #define RK3036_PLLCON1_REFDIV_SHIFT 0
28 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6
29 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6
30 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12
31 #define RK3036_PLLCON1_DSMPD_SHIFT 12
32 #define RK3036_PLLCON2_FRAC_MASK 0xffffff
33 #define RK3036_PLLCON2_FRAC_SHIFT 0
34 #define RK3036_PLLCON1_PWRDOWN_SHIT 13
35
36 #define MHZ 1000000
37 #define KHZ 1000
38 enum {
39 OSC_HZ = 24 * 1000000,
40 VCO_MAX_HZ = 3200U * 1000000,
41 VCO_MIN_HZ = 800 * 1000000,
42 OUTPUT_MAX_HZ = 3200U * 1000000,
43 OUTPUT_MIN_HZ = 24 * 1000000,
44 };
45
46 #define MIN_FOUTVCO_FREQ (800 * MHZ)
47 #define MAX_FOUTVCO_FREQ (2000 * MHZ)
48
gcd(int m,int n)49 int gcd(int m, int n)
50 {
51 int t;
52
53 while (m > 0) {
54 if (n > m) {
55 t = m;
56 m = n;
57 n = t;
58 } /* swap */
59 m -= n;
60 }
61 return n;
62 }
63
64 /*
65 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
66 * Formulas also embedded within the Fractional PLL Verilog model:
67 * If DSMPD = 1 (DSM is disabled, "integer mode")
68 * FOUTVCO = FREF / REFDIV * FBDIV
69 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
70 * Where:
71 * FOUTVCO = Fractional PLL non-divided output frequency
72 * FOUTPOSTDIV = Fractional PLL divided output frequency
73 * (output of second post divider)
74 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
75 * REFDIV = Fractional PLL input reference clock divider
76 * FBDIV = Integer value programmed into feedback divide
77 *
78 */
79
rockchip_pll_clk_set_postdiv(ulong fout_hz,u32 * postdiv1,u32 * postdiv2,u32 * foutvco)80 static int rockchip_pll_clk_set_postdiv(ulong fout_hz,
81 u32 *postdiv1,
82 u32 *postdiv2,
83 u32 *foutvco)
84 {
85 ulong freq;
86
87 if (fout_hz < MIN_FOUTVCO_FREQ) {
88 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
89 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
90 freq = fout_hz * (*postdiv1) * (*postdiv2);
91 if (freq >= MIN_FOUTVCO_FREQ &&
92 freq <= MAX_FOUTVCO_FREQ) {
93 *foutvco = freq;
94 return 0;
95 }
96 }
97 }
98 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n",
99 fout_hz);
100 } else {
101 *postdiv1 = 1;
102 *postdiv2 = 1;
103 }
104 return 0;
105 }
106
107 static struct rockchip_pll_rate_table *
rockchip_pll_clk_set_by_auto(ulong fin_hz,ulong fout_hz)108 rockchip_pll_clk_set_by_auto(ulong fin_hz,
109 ulong fout_hz)
110 {
111 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
112 /* FIXME set postdiv1/2 always 1*/
113 u32 foutvco = fout_hz;
114 ulong fin_64, frac_64;
115 u32 f_frac, postdiv1, postdiv2;
116 ulong clk_gcd = 0;
117
118 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
119 return NULL;
120
121 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
122 rate_table->postdiv1 = postdiv1;
123 rate_table->postdiv2 = postdiv2;
124 rate_table->dsmpd = 1;
125
126 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
127 fin_hz /= MHZ;
128 foutvco /= MHZ;
129 clk_gcd = gcd(fin_hz, foutvco);
130 rate_table->refdiv = fin_hz / clk_gcd;
131 rate_table->fbdiv = foutvco / clk_gcd;
132
133 rate_table->frac = 0;
134
135 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n",
136 fin_hz, fout_hz, clk_gcd);
137 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n",
138 rate_table->refdiv,
139 rate_table->fbdiv, rate_table->postdiv1,
140 rate_table->postdiv2);
141 } else {
142 debug("frac div,fin_hz = %ld,fout_hz = %ld\n",
143 fin_hz, fout_hz);
144 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n",
145 rate_table->postdiv1, rate_table->postdiv2, foutvco);
146 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
147 rate_table->refdiv = fin_hz / MHZ / clk_gcd;
148 rate_table->fbdiv = foutvco / MHZ / clk_gcd;
149 debug("frac get refdiv = %d, fbdiv = %d\n",
150 rate_table->refdiv, rate_table->fbdiv);
151
152 rate_table->frac = 0;
153
154 f_frac = (foutvco % MHZ);
155 fin_64 = fin_hz;
156 fin_64 = fin_64 / rate_table->refdiv;
157 frac_64 = f_frac << 24;
158 frac_64 = frac_64 / fin_64;
159 rate_table->frac = frac_64;
160 if (rate_table->frac > 0)
161 rate_table->dsmpd = 0;
162 debug("frac = %x\n", rate_table->frac);
163 }
164 return rate_table;
165 }
166
167 static const struct rockchip_pll_rate_table *
rockchip_get_pll_settings(struct rockchip_pll_clock * pll,ulong rate)168 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
169 {
170 struct rockchip_pll_rate_table *rate_table = pll->rate_table;
171
172 while (rate_table->rate) {
173 if (rate_table->rate == rate)
174 break;
175 rate_table++;
176 }
177 if (rate_table->rate != rate)
178 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
179 else
180 return rate_table;
181 }
182
rk3036_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)183 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
184 void __iomem *base, ulong pll_id,
185 ulong drate)
186 {
187 const struct rockchip_pll_rate_table *rate;
188
189 rate = rockchip_get_pll_settings(pll, drate);
190 if (!rate) {
191 printf("%s unsupport rate\n", __func__);
192 return -EINVAL;
193 }
194
195 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n",
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);
197 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n",
198 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);
199
200 /*
201 * When power on or changing PLL setting,
202 * we must force PLL into slow mode to ensure output stable clock.
203 */
204 rk_clrsetreg(base + pll->mode_offset,
205 pll->mode_mask << pll->mode_shift,
206 RKCLK_PLL_MODE_SLOW << pll->mode_shift);
207
208 /* Power down */
209 rk_setreg(base + pll->con_offset + 0x4,
210 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
211
212 rk_clrsetreg(base + pll->con_offset,
213 (RK3036_PLLCON0_POSTDIV1_MASK |
214 RK3036_PLLCON0_FBDIV_MASK),
215 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |
216 rate->fbdiv);
217 rk_clrsetreg(base + pll->con_offset + 0x4,
218 (RK3036_PLLCON1_POSTDIV2_MASK |
219 RK3036_PLLCON1_REFDIV_MASK),
220 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
221 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
222 if (!rate->dsmpd) {
223 rk_clrsetreg(base + pll->con_offset + 0x4,
224 RK3036_PLLCON1_DSMPD_MASK,
225 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
226 writel((readl(base + pll->con_offset + 0x8) &
227 (~RK3036_PLLCON2_FRAC_MASK)) |
228 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
229 base + pll->con_offset + 0x8);
230 }
231
232 /* Power Up */
233 rk_clrreg(base + pll->con_offset + 0x4,
234 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
235
236 /* waiting for pll lock */
237 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
238 udelay(1);
239
240 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
241 RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
242 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
243 pll, readl(base + pll->con_offset),
244 readl(base + pll->con_offset + 0x4),
245 readl(base + pll->con_offset + 0x8),
246 readl(base + pll->mode_offset));
247
248 return 0;
249 }
250
rk3036_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)251 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
252 void __iomem *base, ulong pll_id)
253 {
254 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
255 u32 con = 0, shift, mask;
256 ulong rate;
257
258 con = readl(base + pll->mode_offset);
259 shift = pll->mode_shift;
260 mask = pll->mode_mask << shift;
261
262 switch ((con & mask) >> shift) {
263 case RKCLK_PLL_MODE_SLOW:
264 return OSC_HZ;
265 case RKCLK_PLL_MODE_NORMAL:
266 /* normal mode */
267 con = readl(base + pll->con_offset);
268 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >>
269 RK3036_PLLCON0_POSTDIV1_SHIFT;
270 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >>
271 RK3036_PLLCON0_FBDIV_SHIFT;
272 con = readl(base + pll->con_offset + 0x4);
273 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >>
274 RK3036_PLLCON1_POSTDIV2_SHIFT;
275 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >>
276 RK3036_PLLCON1_REFDIV_SHIFT;
277 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >>
278 RK3036_PLLCON1_DSMPD_SHIFT;
279 con = readl(base + pll->con_offset + 0x8);
280 frac = (con & RK3036_PLLCON2_FRAC_MASK) >>
281 RK3036_PLLCON2_FRAC_SHIFT;
282 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
283 if (dsmpd == 0) {
284 u64 frac_rate = OSC_HZ * (u64)frac;
285
286 do_div(frac_rate, refdiv);
287 frac_rate >>= 24;
288 do_div(frac_rate, postdiv1);
289 do_div(frac_rate, postdiv1);
290 rate += frac_rate;
291 }
292 return rate;
293 case RKCLK_PLL_MODE_DEEP:
294 default:
295 return 32768;
296 }
297 }
298
rockchip_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)299 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
300 void __iomem *base,
301 ulong pll_id)
302 {
303 ulong rate = 0;
304
305 switch (pll->type) {
306 case pll_rk3036:
307 pll->mode_mask = PLL_MODE_MASK;
308 rate = rk3036_pll_get_rate(pll, base, pll_id);
309 break;
310 case pll_rk3328:
311 pll->mode_mask = PLL_RK3328_MODE_MASK;
312 rate = rk3036_pll_get_rate(pll, base, pll_id);
313 break;
314 default:
315 printf("%s: Unknown pll type for pll clk %ld\n",
316 __func__, pll_id);
317 }
318 return rate;
319 }
320
rockchip_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)321 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
322 void __iomem *base, ulong pll_id,
323 ulong drate)
324 {
325 int ret = 0;
326
327 if (rockchip_pll_get_rate(pll, base, pll_id) == drate)
328 return 0;
329
330 switch (pll->type) {
331 case pll_rk3036:
332 pll->mode_mask = PLL_MODE_MASK;
333 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
334 break;
335 case pll_rk3328:
336 pll->mode_mask = PLL_RK3328_MODE_MASK;
337 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
338 break;
339 default:
340 printf("%s: Unknown pll type for pll clk %ld\n",
341 __func__, pll_id);
342 }
343 return ret;
344 }
345
346 const struct rockchip_cpu_rate_table *
rockchip_get_cpu_settings(struct rockchip_cpu_rate_table * cpu_table,ulong rate)347 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
348 ulong rate)
349 {
350 struct rockchip_cpu_rate_table *ps = cpu_table;
351
352 while (ps->rate) {
353 if (ps->rate == rate)
354 break;
355 ps++;
356 }
357 if (ps->rate != rate)
358 return NULL;
359 else
360 return ps;
361 }
362
363