1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <mmc.h>
17 #include <sdhci.h>
18 #include <asm/cache.h>
19 #include <linux/bitops.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <phys2bus.h>
23 #include <power/regulator.h>
24
sdhci_reset(struct sdhci_host * host,u8 mask)25 static void sdhci_reset(struct sdhci_host *host, u8 mask)
26 {
27 unsigned long timeout;
28
29 /* Wait max 100 ms */
30 timeout = 100;
31 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
32 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
33 if (timeout == 0) {
34 printf("%s: Reset 0x%x never completed.\n",
35 __func__, (int)mask);
36 return;
37 }
38 timeout--;
39 udelay(1000);
40 }
41 }
42
sdhci_cmd_done(struct sdhci_host * host,struct mmc_cmd * cmd)43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
44 {
45 int i;
46 if (cmd->resp_type & MMC_RSP_136) {
47 /* CRC is stripped so we need to do some shifting. */
48 for (i = 0; i < 4; i++) {
49 cmd->response[i] = sdhci_readl(host,
50 SDHCI_RESPONSE + (3-i)*4) << 8;
51 if (i != 3)
52 cmd->response[i] |= sdhci_readb(host,
53 SDHCI_RESPONSE + (3-i)*4-1);
54 }
55 } else {
56 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
57 }
58 }
59
sdhci_transfer_pio(struct sdhci_host * host,struct mmc_data * data)60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
61 {
62 int i;
63 char *offs;
64 for (i = 0; i < data->blocksize; i += 4) {
65 offs = data->dest + i;
66 if (data->flags == MMC_DATA_READ)
67 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
68 else
69 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
70 }
71 }
72
73 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
sdhci_prepare_dma(struct sdhci_host * host,struct mmc_data * data,int * is_aligned,int trans_bytes)74 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
75 int *is_aligned, int trans_bytes)
76 {
77 dma_addr_t dma_addr;
78 unsigned char ctrl;
79 void *buf;
80
81 if (data->flags == MMC_DATA_READ)
82 buf = data->dest;
83 else
84 buf = (void *)data->src;
85
86 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
87 ctrl &= ~SDHCI_CTRL_DMA_MASK;
88 if (host->flags & USE_ADMA64)
89 ctrl |= SDHCI_CTRL_ADMA64;
90 else if (host->flags & USE_ADMA)
91 ctrl |= SDHCI_CTRL_ADMA32;
92 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
93
94 if (host->flags & USE_SDMA &&
95 (host->force_align_buffer ||
96 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
97 ((unsigned long)buf & 0x7) != 0x0))) {
98 *is_aligned = 0;
99 if (data->flags != MMC_DATA_READ)
100 memcpy(host->align_buffer, buf, trans_bytes);
101 buf = host->align_buffer;
102 }
103
104 host->start_addr = dma_map_single(buf, trans_bytes,
105 mmc_get_dma_dir(data));
106
107 if (host->flags & USE_SDMA) {
108 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
109 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
110 }
111 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
112 else if (host->flags & (USE_ADMA | USE_ADMA64)) {
113 sdhci_prepare_adma_table(host->adma_desc_table, data,
114 host->start_addr);
115
116 sdhci_writel(host, lower_32_bits(host->adma_addr),
117 SDHCI_ADMA_ADDRESS);
118 if (host->flags & USE_ADMA64)
119 sdhci_writel(host, upper_32_bits(host->adma_addr),
120 SDHCI_ADMA_ADDRESS_HI);
121 }
122 #endif
123 }
124 #else
sdhci_prepare_dma(struct sdhci_host * host,struct mmc_data * data,int * is_aligned,int trans_bytes)125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
126 int *is_aligned, int trans_bytes)
127 {}
128 #endif
sdhci_transfer_data(struct sdhci_host * host,struct mmc_data * data)129 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
130 {
131 dma_addr_t start_addr = host->start_addr;
132 unsigned int stat, rdy, mask, timeout, block = 0;
133 bool transfer_done = false;
134
135 timeout = 1000000;
136 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
137 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
138 do {
139 stat = sdhci_readl(host, SDHCI_INT_STATUS);
140 if (stat & SDHCI_INT_ERROR) {
141 pr_debug("%s: Error detected in status(0x%X)!\n",
142 __func__, stat);
143 return -EIO;
144 }
145 if (!transfer_done && (stat & rdy)) {
146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
147 continue;
148 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
149 sdhci_transfer_pio(host, data);
150 data->dest += data->blocksize;
151 if (++block >= data->blocks) {
152 /* Keep looping until the SDHCI_INT_DATA_END is
153 * cleared, even if we finished sending all the
154 * blocks.
155 */
156 transfer_done = true;
157 continue;
158 }
159 }
160 if ((host->flags & USE_DMA) && !transfer_done &&
161 (stat & SDHCI_INT_DMA_END)) {
162 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
163 if (host->flags & USE_SDMA) {
164 start_addr &=
165 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
166 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
167 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
168 start_addr);
169 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
170 }
171 }
172 if (timeout-- > 0)
173 udelay(10);
174 else {
175 printf("%s: Transfer data timeout\n", __func__);
176 return -ETIMEDOUT;
177 }
178 } while (!(stat & SDHCI_INT_DATA_END));
179
180 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
181 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
182 mmc_get_dma_dir(data));
183 #endif
184
185 return 0;
186 }
187
188 /*
189 * No command will be sent by driver if card is busy, so driver must wait
190 * for card ready state.
191 * Every time when card is busy after timeout then (last) timeout value will be
192 * increased twice but only if it doesn't exceed global defined maximum.
193 * Each function call will use last timeout value.
194 */
195 #define SDHCI_CMD_MAX_TIMEOUT 3200
196 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
197 #define SDHCI_READ_STATUS_TIMEOUT 1000
198
199 #ifdef CONFIG_DM_MMC
sdhci_send_command(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)200 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
201 struct mmc_data *data)
202 {
203 struct mmc *mmc = mmc_get_mmc_dev(dev);
204
205 #else
206 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
207 struct mmc_data *data)
208 {
209 #endif
210 struct sdhci_host *host = mmc->priv;
211 unsigned int stat = 0;
212 int ret = 0;
213 int trans_bytes = 0, is_aligned = 1;
214 u32 mask, flags, mode;
215 unsigned int time = 0;
216 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
217 ulong start = get_timer(0);
218
219 host->start_addr = 0;
220 /* Timeout unit - ms */
221 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
222
223 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
224
225 /* We shouldn't wait for data inihibit for stop commands, even
226 though they might use busy signaling */
227 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
228 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
229 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
230 mask &= ~SDHCI_DATA_INHIBIT;
231
232 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
233 if (time >= cmd_timeout) {
234 printf("%s: MMC: %d busy ", __func__, mmc_dev);
235 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
236 cmd_timeout += cmd_timeout;
237 printf("timeout increasing to: %u ms.\n",
238 cmd_timeout);
239 } else {
240 puts("timeout.\n");
241 return -ECOMM;
242 }
243 }
244 time++;
245 udelay(1000);
246 }
247
248 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
249
250 mask = SDHCI_INT_RESPONSE;
251 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
252 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
253 mask = SDHCI_INT_DATA_AVAIL;
254
255 if (!(cmd->resp_type & MMC_RSP_PRESENT))
256 flags = SDHCI_CMD_RESP_NONE;
257 else if (cmd->resp_type & MMC_RSP_136)
258 flags = SDHCI_CMD_RESP_LONG;
259 else if (cmd->resp_type & MMC_RSP_BUSY) {
260 flags = SDHCI_CMD_RESP_SHORT_BUSY;
261 if (data)
262 mask |= SDHCI_INT_DATA_END;
263 } else
264 flags = SDHCI_CMD_RESP_SHORT;
265
266 if (cmd->resp_type & MMC_RSP_CRC)
267 flags |= SDHCI_CMD_CRC;
268 if (cmd->resp_type & MMC_RSP_OPCODE)
269 flags |= SDHCI_CMD_INDEX;
270 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
271 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
272 flags |= SDHCI_CMD_DATA;
273
274 /* Set Transfer mode regarding to data flag */
275 if (data) {
276 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
277 mode = SDHCI_TRNS_BLK_CNT_EN;
278 trans_bytes = data->blocks * data->blocksize;
279 if (data->blocks > 1)
280 mode |= SDHCI_TRNS_MULTI;
281
282 if (data->flags == MMC_DATA_READ)
283 mode |= SDHCI_TRNS_READ;
284
285 if (host->flags & USE_DMA) {
286 mode |= SDHCI_TRNS_DMA;
287 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
288 }
289
290 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
291 data->blocksize),
292 SDHCI_BLOCK_SIZE);
293 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
294 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
295 } else if (cmd->resp_type & MMC_RSP_BUSY) {
296 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
297 }
298
299 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
300 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
301 start = get_timer(0);
302 do {
303 stat = sdhci_readl(host, SDHCI_INT_STATUS);
304 if (stat & SDHCI_INT_ERROR)
305 break;
306
307 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
308 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
309 return 0;
310 } else {
311 printf("%s: Timeout for status update!\n",
312 __func__);
313 return -ETIMEDOUT;
314 }
315 }
316 } while ((stat & mask) != mask);
317
318 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
319 sdhci_cmd_done(host, cmd);
320 sdhci_writel(host, mask, SDHCI_INT_STATUS);
321 } else
322 ret = -1;
323
324 if (!ret && data)
325 ret = sdhci_transfer_data(host, data);
326
327 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
328 udelay(1000);
329
330 stat = sdhci_readl(host, SDHCI_INT_STATUS);
331 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
332 if (!ret) {
333 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
334 !is_aligned && (data->flags == MMC_DATA_READ))
335 memcpy(data->dest, host->align_buffer, trans_bytes);
336 return 0;
337 }
338
339 sdhci_reset(host, SDHCI_RESET_CMD);
340 sdhci_reset(host, SDHCI_RESET_DATA);
341 if (stat & SDHCI_INT_TIMEOUT)
342 return -ETIMEDOUT;
343 else
344 return -ECOMM;
345 }
346
347 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
348 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
349 {
350 int err;
351 struct mmc *mmc = mmc_get_mmc_dev(dev);
352 struct sdhci_host *host = mmc->priv;
353
354 debug("%s\n", __func__);
355
356 if (host->ops && host->ops->platform_execute_tuning) {
357 err = host->ops->platform_execute_tuning(mmc, opcode);
358 if (err)
359 return err;
360 return 0;
361 }
362 return 0;
363 }
364 #endif
365 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
366 {
367 struct sdhci_host *host = mmc->priv;
368 unsigned int div, clk = 0, timeout;
369
370 /* Wait max 20 ms */
371 timeout = 200;
372 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
373 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
374 if (timeout == 0) {
375 printf("%s: Timeout to wait cmd & data inhibit\n",
376 __func__);
377 return -EBUSY;
378 }
379
380 timeout--;
381 udelay(100);
382 }
383
384 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
385
386 if (clock == 0)
387 return 0;
388
389 if (host->ops && host->ops->set_delay)
390 host->ops->set_delay(host);
391
392 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
393 /*
394 * Check if the Host Controller supports Programmable Clock
395 * Mode.
396 */
397 if (host->clk_mul) {
398 for (div = 1; div <= 1024; div++) {
399 if ((host->max_clk / div) <= clock)
400 break;
401 }
402
403 /*
404 * Set Programmable Clock Mode in the Clock
405 * Control register.
406 */
407 clk = SDHCI_PROG_CLOCK_MODE;
408 div--;
409 } else {
410 /* Version 3.00 divisors must be a multiple of 2. */
411 if (host->max_clk <= clock) {
412 div = 1;
413 } else {
414 for (div = 2;
415 div < SDHCI_MAX_DIV_SPEC_300;
416 div += 2) {
417 if ((host->max_clk / div) <= clock)
418 break;
419 }
420 }
421 div >>= 1;
422 }
423 } else {
424 /* Version 2.00 divisors must be a power of 2. */
425 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
426 if ((host->max_clk / div) <= clock)
427 break;
428 }
429 div >>= 1;
430 }
431
432 if (host->ops && host->ops->set_clock)
433 host->ops->set_clock(host, div);
434
435 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
436 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
437 << SDHCI_DIVIDER_HI_SHIFT;
438 clk |= SDHCI_CLOCK_INT_EN;
439 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
440
441 /* Wait max 20 ms */
442 timeout = 20;
443 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
444 & SDHCI_CLOCK_INT_STABLE)) {
445 if (timeout == 0) {
446 printf("%s: Internal clock never stabilised.\n",
447 __func__);
448 return -EBUSY;
449 }
450 timeout--;
451 udelay(1000);
452 }
453
454 clk |= SDHCI_CLOCK_CARD_EN;
455 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
456 return 0;
457 }
458
459 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
460 {
461 u8 pwr = 0;
462
463 if (power != (unsigned short)-1) {
464 switch (1 << power) {
465 case MMC_VDD_165_195:
466 pwr = SDHCI_POWER_180;
467 break;
468 case MMC_VDD_29_30:
469 case MMC_VDD_30_31:
470 pwr = SDHCI_POWER_300;
471 break;
472 case MMC_VDD_32_33:
473 case MMC_VDD_33_34:
474 pwr = SDHCI_POWER_330;
475 break;
476 }
477 }
478
479 if (pwr == 0) {
480 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
481 return;
482 }
483
484 pwr |= SDHCI_POWER_ON;
485
486 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
487 }
488
489 void sdhci_set_uhs_timing(struct sdhci_host *host)
490 {
491 struct mmc *mmc = host->mmc;
492 u32 reg;
493
494 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
495 reg &= ~SDHCI_CTRL_UHS_MASK;
496
497 switch (mmc->selected_mode) {
498 case UHS_SDR50:
499 case MMC_HS_52:
500 reg |= SDHCI_CTRL_UHS_SDR50;
501 break;
502 case UHS_DDR50:
503 case MMC_DDR_52:
504 reg |= SDHCI_CTRL_UHS_DDR50;
505 break;
506 case UHS_SDR104:
507 case MMC_HS_200:
508 reg |= SDHCI_CTRL_UHS_SDR104;
509 break;
510 default:
511 reg |= SDHCI_CTRL_UHS_SDR12;
512 }
513
514 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
515 }
516
517 static void sdhci_set_voltage(struct sdhci_host *host)
518 {
519 if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
520 struct mmc *mmc = (struct mmc *)host->mmc;
521 u32 ctrl;
522
523 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
524
525 switch (mmc->signal_voltage) {
526 case MMC_SIGNAL_VOLTAGE_330:
527 #if CONFIG_IS_ENABLED(DM_REGULATOR)
528 if (mmc->vqmmc_supply) {
529 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
530 pr_err("failed to disable vqmmc-supply\n");
531 return;
532 }
533
534 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
535 pr_err("failed to set vqmmc-voltage to 3.3V\n");
536 return;
537 }
538
539 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
540 pr_err("failed to enable vqmmc-supply\n");
541 return;
542 }
543 }
544 #endif
545 if (IS_SD(mmc)) {
546 ctrl &= ~SDHCI_CTRL_VDD_180;
547 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
548 }
549
550 /* Wait for 5ms */
551 mdelay(5);
552
553 /* 3.3V regulator output should be stable within 5 ms */
554 if (IS_SD(mmc)) {
555 if (ctrl & SDHCI_CTRL_VDD_180) {
556 pr_err("3.3V regulator output did not become stable\n");
557 return;
558 }
559 }
560
561 break;
562 case MMC_SIGNAL_VOLTAGE_180:
563 #if CONFIG_IS_ENABLED(DM_REGULATOR)
564 if (mmc->vqmmc_supply) {
565 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
566 pr_err("failed to disable vqmmc-supply\n");
567 return;
568 }
569
570 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
571 pr_err("failed to set vqmmc-voltage to 1.8V\n");
572 return;
573 }
574
575 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
576 pr_err("failed to enable vqmmc-supply\n");
577 return;
578 }
579 }
580 #endif
581 if (IS_SD(mmc)) {
582 ctrl |= SDHCI_CTRL_VDD_180;
583 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
584 }
585
586 /* Wait for 5 ms */
587 mdelay(5);
588
589 /* 1.8V regulator output has to be stable within 5 ms */
590 if (IS_SD(mmc)) {
591 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
592 pr_err("1.8V regulator output did not become stable\n");
593 return;
594 }
595 }
596
597 break;
598 default:
599 /* No signal voltage switch required */
600 return;
601 }
602 }
603 }
604
605 void sdhci_set_control_reg(struct sdhci_host *host)
606 {
607 sdhci_set_voltage(host);
608 sdhci_set_uhs_timing(host);
609 }
610
611 #ifdef CONFIG_DM_MMC
612 static int sdhci_set_ios(struct udevice *dev)
613 {
614 struct mmc *mmc = mmc_get_mmc_dev(dev);
615 #else
616 static int sdhci_set_ios(struct mmc *mmc)
617 {
618 #endif
619 u32 ctrl;
620 struct sdhci_host *host = mmc->priv;
621 bool no_hispd_bit = false;
622
623 if (host->ops && host->ops->set_control_reg)
624 host->ops->set_control_reg(host);
625
626 if (mmc->clock != host->clock)
627 sdhci_set_clock(mmc, mmc->clock);
628
629 if (mmc->clk_disable)
630 sdhci_set_clock(mmc, 0);
631
632 /* Set bus width */
633 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
634 if (mmc->bus_width == 8) {
635 ctrl &= ~SDHCI_CTRL_4BITBUS;
636 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
637 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
638 ctrl |= SDHCI_CTRL_8BITBUS;
639 } else {
640 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
641 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
642 ctrl &= ~SDHCI_CTRL_8BITBUS;
643 if (mmc->bus_width == 4)
644 ctrl |= SDHCI_CTRL_4BITBUS;
645 else
646 ctrl &= ~SDHCI_CTRL_4BITBUS;
647 }
648
649 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
650 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
651 ctrl &= ~SDHCI_CTRL_HISPD;
652 no_hispd_bit = true;
653 }
654
655 if (!no_hispd_bit) {
656 if (mmc->selected_mode == MMC_HS ||
657 mmc->selected_mode == SD_HS ||
658 mmc->selected_mode == MMC_DDR_52 ||
659 mmc->selected_mode == MMC_HS_200 ||
660 mmc->selected_mode == MMC_HS_400 ||
661 mmc->selected_mode == UHS_SDR25 ||
662 mmc->selected_mode == UHS_SDR50 ||
663 mmc->selected_mode == UHS_SDR104 ||
664 mmc->selected_mode == UHS_DDR50)
665 ctrl |= SDHCI_CTRL_HISPD;
666 else
667 ctrl &= ~SDHCI_CTRL_HISPD;
668 }
669
670 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
671
672 /* If available, call the driver specific "post" set_ios() function */
673 if (host->ops && host->ops->set_ios_post)
674 return host->ops->set_ios_post(host);
675
676 return 0;
677 }
678
679 static int sdhci_init(struct mmc *mmc)
680 {
681 struct sdhci_host *host = mmc->priv;
682 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
683 struct udevice *dev = mmc->dev;
684
685 gpio_request_by_name(dev, "cd-gpios", 0,
686 &host->cd_gpio, GPIOD_IS_IN);
687 #endif
688
689 sdhci_reset(host, SDHCI_RESET_ALL);
690
691 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
692 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
693 /*
694 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
695 * is defined.
696 */
697 host->force_align_buffer = true;
698 #else
699 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
700 host->align_buffer = memalign(8, 512 * 1024);
701 if (!host->align_buffer) {
702 printf("%s: Aligned buffer alloc failed!!!\n",
703 __func__);
704 return -ENOMEM;
705 }
706 }
707 #endif
708
709 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
710
711 if (host->ops && host->ops->get_cd)
712 host->ops->get_cd(host);
713
714 /* Enable only interrupts served by the SD controller */
715 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
716 SDHCI_INT_ENABLE);
717 /* Mask all sdhci interrupt sources */
718 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
719
720 return 0;
721 }
722
723 #ifdef CONFIG_DM_MMC
724 int sdhci_probe(struct udevice *dev)
725 {
726 struct mmc *mmc = mmc_get_mmc_dev(dev);
727
728 return sdhci_init(mmc);
729 }
730
731 static int sdhci_deferred_probe(struct udevice *dev)
732 {
733 int err;
734 struct mmc *mmc = mmc_get_mmc_dev(dev);
735 struct sdhci_host *host = mmc->priv;
736
737 if (host->ops && host->ops->deferred_probe) {
738 err = host->ops->deferred_probe(host);
739 if (err)
740 return err;
741 }
742 return 0;
743 }
744
745 static int sdhci_get_cd(struct udevice *dev)
746 {
747 struct mmc *mmc = mmc_get_mmc_dev(dev);
748 struct sdhci_host *host = mmc->priv;
749 int value;
750
751 /* If nonremovable, assume that the card is always present. */
752 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
753 return 1;
754 /* If polling, assume that the card is always present. */
755 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
756 return 1;
757
758 #if CONFIG_IS_ENABLED(DM_GPIO)
759 value = dm_gpio_get_value(&host->cd_gpio);
760 if (value >= 0) {
761 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
762 return !value;
763 else
764 return value;
765 }
766 #endif
767 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
768 SDHCI_CARD_PRESENT);
769 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
770 return !value;
771 else
772 return value;
773 }
774
775 const struct dm_mmc_ops sdhci_ops = {
776 .send_cmd = sdhci_send_command,
777 .set_ios = sdhci_set_ios,
778 .get_cd = sdhci_get_cd,
779 .deferred_probe = sdhci_deferred_probe,
780 #ifdef MMC_SUPPORTS_TUNING
781 .execute_tuning = sdhci_execute_tuning,
782 #endif
783 };
784 #else
785 static const struct mmc_ops sdhci_ops = {
786 .send_cmd = sdhci_send_command,
787 .set_ios = sdhci_set_ios,
788 .init = sdhci_init,
789 };
790 #endif
791
792 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
793 u32 f_max, u32 f_min)
794 {
795 u32 caps, caps_1 = 0;
796 #if CONFIG_IS_ENABLED(DM_MMC)
797 u64 dt_caps, dt_caps_mask;
798
799 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
800 "sdhci-caps-mask", 0);
801 dt_caps = dev_read_u64_default(host->mmc->dev,
802 "sdhci-caps", 0);
803 caps = ~lower_32_bits(dt_caps_mask) &
804 sdhci_readl(host, SDHCI_CAPABILITIES);
805 caps |= lower_32_bits(dt_caps);
806 #else
807 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
808 #endif
809 debug("%s, caps: 0x%x\n", __func__, caps);
810
811 #ifdef CONFIG_MMC_SDHCI_SDMA
812 if ((caps & SDHCI_CAN_DO_SDMA)) {
813 host->flags |= USE_SDMA;
814 } else {
815 debug("%s: Your controller doesn't support SDMA!!\n",
816 __func__);
817 }
818 #endif
819 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
820 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
821 printf("%s: Your controller doesn't support SDMA!!\n",
822 __func__);
823 return -EINVAL;
824 }
825 host->adma_desc_table = sdhci_adma_init();
826 host->adma_addr = (dma_addr_t)host->adma_desc_table;
827
828 #ifdef CONFIG_DMA_ADDR_T_64BIT
829 host->flags |= USE_ADMA64;
830 #else
831 host->flags |= USE_ADMA;
832 #endif
833 #endif
834 if (host->quirks & SDHCI_QUIRK_REG32_RW)
835 host->version =
836 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
837 else
838 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
839
840 cfg->name = host->name;
841 #ifndef CONFIG_DM_MMC
842 cfg->ops = &sdhci_ops;
843 #endif
844
845 /* Check whether the clock multiplier is supported or not */
846 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
847 #if CONFIG_IS_ENABLED(DM_MMC)
848 caps_1 = ~upper_32_bits(dt_caps_mask) &
849 sdhci_readl(host, SDHCI_CAPABILITIES_1);
850 caps_1 |= upper_32_bits(dt_caps);
851 #else
852 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
853 #endif
854 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
855 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
856 SDHCI_CLOCK_MUL_SHIFT;
857 }
858
859 if (host->max_clk == 0) {
860 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
861 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
862 SDHCI_CLOCK_BASE_SHIFT;
863 else
864 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
865 SDHCI_CLOCK_BASE_SHIFT;
866 host->max_clk *= 1000000;
867 if (host->clk_mul)
868 host->max_clk *= host->clk_mul;
869 }
870 if (host->max_clk == 0) {
871 printf("%s: Hardware doesn't specify base clock frequency\n",
872 __func__);
873 return -EINVAL;
874 }
875 if (f_max && (f_max < host->max_clk))
876 cfg->f_max = f_max;
877 else
878 cfg->f_max = host->max_clk;
879 if (f_min)
880 cfg->f_min = f_min;
881 else {
882 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
883 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
884 else
885 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
886 }
887 cfg->voltages = 0;
888 if (caps & SDHCI_CAN_VDD_330)
889 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
890 if (caps & SDHCI_CAN_VDD_300)
891 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
892 if (caps & SDHCI_CAN_VDD_180)
893 cfg->voltages |= MMC_VDD_165_195;
894
895 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
896 cfg->voltages |= host->voltages;
897
898 if (caps & SDHCI_CAN_DO_HISPD)
899 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
900
901 cfg->host_caps |= MMC_MODE_4BIT;
902
903 /* Since Host Controller Version3.0 */
904 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
905 if (!(caps & SDHCI_CAN_DO_8BIT))
906 cfg->host_caps &= ~MMC_MODE_8BIT;
907 }
908
909 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
910 cfg->host_caps &= ~MMC_MODE_HS;
911 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
912 }
913
914 if (!(cfg->voltages & MMC_VDD_165_195) ||
915 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
916 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
917 SDHCI_SUPPORT_DDR50);
918
919 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
920 SDHCI_SUPPORT_DDR50))
921 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
922
923 if (caps_1 & SDHCI_SUPPORT_SDR104) {
924 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
925 /*
926 * SD3.0: SDR104 is supported so (for eMMC) the caps2
927 * field can be promoted to support HS200.
928 */
929 cfg->host_caps |= MMC_CAP(MMC_HS_200);
930 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
931 cfg->host_caps |= MMC_CAP(UHS_SDR50);
932 }
933
934 if (caps_1 & SDHCI_SUPPORT_DDR50)
935 cfg->host_caps |= MMC_CAP(UHS_DDR50);
936
937 if (host->host_caps)
938 cfg->host_caps |= host->host_caps;
939
940 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
941
942 return 0;
943 }
944
945 #ifdef CONFIG_BLK
946 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
947 {
948 return mmc_bind(dev, mmc, cfg);
949 }
950 #else
951 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
952 {
953 int ret;
954
955 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
956 if (ret)
957 return ret;
958
959 host->mmc = mmc_create(&host->cfg, host);
960 if (host->mmc == NULL) {
961 printf("%s: mmc create fail!\n", __func__);
962 return -ENOMEM;
963 }
964
965 return 0;
966 }
967 #endif
968