1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DDR_H 9 #define DDR_H 10 11 #include "ddr_io.h" 12 #include "dimm.h" 13 #include "immap.h" 14 15 #ifndef DDRC_NUM_CS 16 #define DDRC_NUM_CS 4 17 #endif 18 19 /* 20 * This is irrespective of what is the number of DDR controller, 21 * number of DIMM used. This is set to maximum 22 * Max controllers = 2 23 * Max num of DIMM per controlle = 2 24 * MAX NUM CS = 4 25 * Not to be changed. 26 */ 27 #define MAX_DDRC_NUM 2 28 #define MAX_DIMM_NUM 2 29 #define MAX_CS_NUM 4 30 31 #include "opts.h" 32 #include "regs.h" 33 #include "utility.h" 34 35 #ifdef DDR_DEBUG 36 #define debug(...) INFO(__VA_ARGS__) 37 #else 38 #define debug(...) VERBOSE(__VA_ARGS__) 39 #endif 40 41 #ifndef DDRC_NUM_DIMM 42 #define DDRC_NUM_DIMM 1 43 #endif 44 45 #define CONFIG_CS_PER_SLOT \ 46 (DDRC_NUM_CS / DDRC_NUM_DIMM) 47 48 /* Record of register values computed */ 49 struct ddr_cfg_regs { 50 struct { 51 unsigned int bnds; 52 unsigned int config; 53 unsigned int config_2; 54 } cs[MAX_CS_NUM]; 55 unsigned int dec[10]; 56 unsigned int timing_cfg[10]; 57 unsigned int sdram_cfg[3]; 58 unsigned int sdram_mode[16]; 59 unsigned int md_cntl; 60 unsigned int interval; 61 unsigned int data_init; 62 unsigned int clk_cntl; 63 unsigned int init_addr; 64 unsigned int init_ext_addr; 65 unsigned int zq_cntl; 66 unsigned int wrlvl_cntl[3]; 67 unsigned int ddr_sr_cntr; 68 unsigned int sdram_rcw[6]; 69 unsigned int dq_map[4]; 70 unsigned int eor; 71 unsigned int cdr[2]; 72 unsigned int err_disable; 73 unsigned int err_int_en; 74 unsigned int tx_cfg[4]; 75 unsigned int debug[64]; 76 }; 77 78 struct ddr_conf { 79 int dimm_in_use[MAX_DIMM_NUM]; 80 int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */ 81 int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */ 82 unsigned long long cs_base_addr[MAX_CS_NUM]; 83 unsigned long long cs_size[MAX_CS_NUM]; 84 unsigned long long base_addr; 85 unsigned long long total_mem; 86 }; 87 88 struct ddr_info { 89 unsigned long clk; 90 unsigned long long mem_base; 91 unsigned int num_ctlrs; 92 unsigned int dimm_on_ctlr; 93 struct dimm_params dimm; 94 struct memctl_opt opt; 95 struct ddr_conf conf; 96 struct ddr_cfg_regs ddr_reg; 97 struct ccsr_ddr *ddr[MAX_DDRC_NUM]; 98 uint16_t *phy[MAX_DDRC_NUM]; 99 int *spd_addr; 100 unsigned int ip_rev; 101 uintptr_t phy_gen2_fw_img_buf; 102 void *img_loadr; 103 int warm_boot_flag; 104 }; 105 106 struct rc_timing { 107 unsigned int speed_bin; 108 unsigned int clk_adj; 109 unsigned int wrlvl; 110 }; 111 112 struct board_timing { 113 unsigned int rc; 114 struct rc_timing const *p; 115 unsigned int add1; 116 unsigned int add2; 117 }; 118 119 enum warm_boot { 120 DDR_COLD_BOOT = 0, 121 DDR_WARM_BOOT = 1, 122 DDR_WRM_BOOT_NT_SUPPORTED = -1, 123 }; 124 125 int disable_unused_ddrc(struct ddr_info *priv, int mask, 126 uintptr_t nxp_ccn_hn_f0_addr); 127 int ddr_board_options(struct ddr_info *priv); 128 int compute_ddrc(const unsigned long clk, 129 const struct memctl_opt *popts, 130 const struct ddr_conf *conf, 131 struct ddr_cfg_regs *ddr, 132 const struct dimm_params *dimm_params, 133 const unsigned int ip_rev); 134 int compute_ddr_phy(struct ddr_info *priv); 135 int ddrc_set_regs(const unsigned long clk, 136 const struct ddr_cfg_regs *regs, 137 const struct ccsr_ddr *ddr, 138 int twopass); 139 int cal_board_params(struct ddr_info *priv, 140 const struct board_timing *dimm, 141 int len); 142 /* return bit mask of used DIMM(s) */ 143 int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf); 144 long long dram_init(struct ddr_info *priv 145 #if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) 146 , uintptr_t nxp_ccn_hn_f0_addr 147 #endif 148 ); 149 long long board_static_ddr(struct ddr_info *info); 150 151 #endif /* DDR_H */ 152