1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9 #ifndef __SDHCI_HW_H
10 #define __SDHCI_HW_H
11
12 #include <linux/bitops.h>
13 #include <linux/types.h>
14 #include <asm/io.h>
15 #include <mmc.h>
16 #include <asm/gpio.h>
17
18 /*
19 * Controller registers
20 */
21
22 #define SDHCI_DMA_ADDRESS 0x00
23
24 #define SDHCI_BLOCK_SIZE 0x04
25 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
26
27 #define SDHCI_BLOCK_COUNT 0x06
28
29 #define SDHCI_ARGUMENT 0x08
30
31 #define SDHCI_TRANSFER_MODE 0x0C
32 #define SDHCI_TRNS_DMA BIT(0)
33 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
34 #define SDHCI_TRNS_ACMD12 BIT(2)
35 #define SDHCI_TRNS_READ BIT(4)
36 #define SDHCI_TRNS_MULTI BIT(5)
37
38 #define SDHCI_COMMAND 0x0E
39 #define SDHCI_CMD_RESP_MASK 0x03
40 #define SDHCI_CMD_CRC 0x08
41 #define SDHCI_CMD_INDEX 0x10
42 #define SDHCI_CMD_DATA 0x20
43 #define SDHCI_CMD_ABORTCMD 0xC0
44
45 #define SDHCI_CMD_RESP_NONE 0x00
46 #define SDHCI_CMD_RESP_LONG 0x01
47 #define SDHCI_CMD_RESP_SHORT 0x02
48 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
49
50 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
51 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
52
53 #define SDHCI_RESPONSE 0x10
54
55 #define SDHCI_BUFFER 0x20
56
57 #define SDHCI_PRESENT_STATE 0x24
58 #define SDHCI_CMD_INHIBIT BIT(0)
59 #define SDHCI_DATA_INHIBIT BIT(1)
60 #define SDHCI_DOING_WRITE BIT(8)
61 #define SDHCI_DOING_READ BIT(9)
62 #define SDHCI_SPACE_AVAILABLE BIT(10)
63 #define SDHCI_DATA_AVAILABLE BIT(11)
64 #define SDHCI_CARD_PRESENT BIT(16)
65 #define SDHCI_CARD_STATE_STABLE BIT(17)
66 #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
67 #define SDHCI_WRITE_PROTECT BIT(19)
68
69 #define SDHCI_HOST_CONTROL 0x28
70 #define SDHCI_CTRL_LED BIT(0)
71 #define SDHCI_CTRL_4BITBUS BIT(1)
72 #define SDHCI_CTRL_HISPD BIT(2)
73 #define SDHCI_CTRL_DMA_MASK 0x18
74 #define SDHCI_CTRL_SDMA 0x00
75 #define SDHCI_CTRL_ADMA1 0x08
76 #define SDHCI_CTRL_ADMA32 0x10
77 #define SDHCI_CTRL_ADMA64 0x18
78 #define SDHCI_CTRL_8BITBUS BIT(5)
79 #define SDHCI_CTRL_CD_TEST_INS BIT(6)
80 #define SDHCI_CTRL_CD_TEST BIT(7)
81
82 #define SDHCI_POWER_CONTROL 0x29
83 #define SDHCI_POWER_ON 0x01
84 #define SDHCI_POWER_180 0x0A
85 #define SDHCI_POWER_300 0x0C
86 #define SDHCI_POWER_330 0x0E
87
88 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
89
90 #define SDHCI_WAKE_UP_CONTROL 0x2B
91 #define SDHCI_WAKE_ON_INT BIT(0)
92 #define SDHCI_WAKE_ON_INSERT BIT(1)
93 #define SDHCI_WAKE_ON_REMOVE BIT(2)
94
95 #define SDHCI_CLOCK_CONTROL 0x2C
96 #define SDHCI_DIVIDER_SHIFT 8
97 #define SDHCI_DIVIDER_HI_SHIFT 6
98 #define SDHCI_DIV_MASK 0xFF
99 #define SDHCI_DIV_MASK_LEN 8
100 #define SDHCI_DIV_HI_MASK 0x300
101 #define SDHCI_PROG_CLOCK_MODE BIT(5)
102 #define SDHCI_CLOCK_CARD_EN BIT(2)
103 #define SDHCI_CLOCK_INT_STABLE BIT(1)
104 #define SDHCI_CLOCK_INT_EN BIT(0)
105
106 #define SDHCI_TIMEOUT_CONTROL 0x2E
107
108 #define SDHCI_SOFTWARE_RESET 0x2F
109 #define SDHCI_RESET_ALL 0x01
110 #define SDHCI_RESET_CMD 0x02
111 #define SDHCI_RESET_DATA 0x04
112
113 #define SDHCI_INT_STATUS 0x30
114 #define SDHCI_INT_ENABLE 0x34
115 #define SDHCI_SIGNAL_ENABLE 0x38
116 #define SDHCI_INT_RESPONSE BIT(0)
117 #define SDHCI_INT_DATA_END BIT(1)
118 #define SDHCI_INT_DMA_END BIT(3)
119 #define SDHCI_INT_SPACE_AVAIL BIT(4)
120 #define SDHCI_INT_DATA_AVAIL BIT(5)
121 #define SDHCI_INT_CARD_INSERT BIT(6)
122 #define SDHCI_INT_CARD_REMOVE BIT(7)
123 #define SDHCI_INT_CARD_INT BIT(8)
124 #define SDHCI_INT_ERROR BIT(15)
125 #define SDHCI_INT_TIMEOUT BIT(16)
126 #define SDHCI_INT_CRC BIT(17)
127 #define SDHCI_INT_END_BIT BIT(18)
128 #define SDHCI_INT_INDEX BIT(19)
129 #define SDHCI_INT_DATA_TIMEOUT BIT(20)
130 #define SDHCI_INT_DATA_CRC BIT(21)
131 #define SDHCI_INT_DATA_END_BIT BIT(22)
132 #define SDHCI_INT_BUS_POWER BIT(23)
133 #define SDHCI_INT_ACMD12ERR BIT(24)
134 #define SDHCI_INT_ADMA_ERROR BIT(25)
135
136 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
137 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
138
139 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
140 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
141 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
142 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
143 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
144 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
145 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
146
147 #define SDHCI_ACMD12_ERR 0x3C
148
149 #define SDHCI_HOST_CONTROL2 0x3E
150 #define SDHCI_CTRL_UHS_MASK 0x0007
151 #define SDHCI_CTRL_UHS_SDR12 0x0000
152 #define SDHCI_CTRL_UHS_SDR25 0x0001
153 #define SDHCI_CTRL_UHS_SDR50 0x0002
154 #define SDHCI_CTRL_UHS_SDR104 0x0003
155 #define SDHCI_CTRL_UHS_DDR50 0x0004
156 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
157 #define SDHCI_CTRL_VDD_180 0x0008
158 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
159 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
160 #define SDHCI_CTRL_DRV_TYPE_A 0x0010
161 #define SDHCI_CTRL_DRV_TYPE_C 0x0020
162 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
163 #define SDHCI_CTRL_EXEC_TUNING 0x0040
164 #define SDHCI_CTRL_TUNED_CLK 0x0080
165 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
166
167 #define SDHCI_CAPABILITIES 0x40
168 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
169 #define SDHCI_TIMEOUT_CLK_SHIFT 0
170 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
171 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
172 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
173 #define SDHCI_CLOCK_BASE_SHIFT 8
174 #define SDHCI_MAX_BLOCK_MASK 0x00030000
175 #define SDHCI_MAX_BLOCK_SHIFT 16
176 #define SDHCI_CAN_DO_8BIT BIT(18)
177 #define SDHCI_CAN_DO_ADMA2 BIT(19)
178 #define SDHCI_CAN_DO_ADMA1 BIT(20)
179 #define SDHCI_CAN_DO_HISPD BIT(21)
180 #define SDHCI_CAN_DO_SDMA BIT(22)
181 #define SDHCI_CAN_VDD_330 BIT(24)
182 #define SDHCI_CAN_VDD_300 BIT(25)
183 #define SDHCI_CAN_VDD_180 BIT(26)
184 #define SDHCI_CAN_64BIT BIT(28)
185
186 #define SDHCI_CAPABILITIES_1 0x44
187 #define SDHCI_SUPPORT_SDR50 0x00000001
188 #define SDHCI_SUPPORT_SDR104 0x00000002
189 #define SDHCI_SUPPORT_DDR50 0x00000004
190 #define SDHCI_USE_SDR50_TUNING 0x00002000
191
192 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
193 #define SDHCI_CLOCK_MUL_SHIFT 16
194
195 #define SDHCI_MAX_CURRENT 0x48
196
197 /* 4C-4F reserved for more max current */
198
199 #define SDHCI_SET_ACMD12_ERROR 0x50
200 #define SDHCI_SET_INT_ERROR 0x52
201
202 #define SDHCI_ADMA_ERROR 0x54
203
204 /* 55-57 reserved */
205
206 #define SDHCI_ADMA_ADDRESS 0x58
207 #define SDHCI_ADMA_ADDRESS_HI 0x5c
208
209 /* 60-FB reserved */
210
211 #define SDHCI_SLOT_INT_STATUS 0xFC
212
213 #define SDHCI_HOST_VERSION 0xFE
214 #define SDHCI_VENDOR_VER_MASK 0xFF00
215 #define SDHCI_VENDOR_VER_SHIFT 8
216 #define SDHCI_SPEC_VER_MASK 0x00FF
217 #define SDHCI_SPEC_VER_SHIFT 0
218 #define SDHCI_SPEC_100 0
219 #define SDHCI_SPEC_200 1
220 #define SDHCI_SPEC_300 2
221
222 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
223
224 /*
225 * End of controller registers.
226 */
227
228 #define SDHCI_MAX_DIV_SPEC_200 256
229 #define SDHCI_MAX_DIV_SPEC_300 2046
230
231 /*
232 * quirks
233 */
234 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
235 #define SDHCI_QUIRK_REG32_RW (1 << 1)
236 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
237 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
238 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
239 /*
240 * SDHCI_QUIRK_BROKEN_HISPD_MODE
241 * the hardware cannot operate correctly in high-speed mode,
242 * this quirk forces the sdhci host-controller to non high-speed mode
243 */
244 #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
245 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
246 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
247 #define SDHCI_QUIRK_NO_1_8_V (1 << 9)
248
249 /* to make gcc happy */
250 struct sdhci_host;
251
252 /*
253 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
254 */
255 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
256 #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
257 struct sdhci_ops {
258 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
259 u32 (*read_l)(struct sdhci_host *host, int reg);
260 u16 (*read_w)(struct sdhci_host *host, int reg);
261 u8 (*read_b)(struct sdhci_host *host, int reg);
262 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
263 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
264 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
265 #endif
266 int (*get_cd)(struct sdhci_host *host);
267 void (*set_control_reg)(struct sdhci_host *host);
268 int (*set_ios_post)(struct sdhci_host *host);
269 void (*set_clock)(struct sdhci_host *host, u32 div);
270 int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
271 void (*set_delay)(struct sdhci_host *host);
272 int (*deferred_probe)(struct sdhci_host *host);
273 };
274
275 #define ADMA_MAX_LEN 65532
276 #ifdef CONFIG_DMA_ADDR_T_64BIT
277 #define ADMA_DESC_LEN 16
278 #else
279 #define ADMA_DESC_LEN 8
280 #endif
281 #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
282 MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
283
284 #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
285
286 /* Decriptor table defines */
287 #define ADMA_DESC_ATTR_VALID BIT(0)
288 #define ADMA_DESC_ATTR_END BIT(1)
289 #define ADMA_DESC_ATTR_INT BIT(2)
290 #define ADMA_DESC_ATTR_ACT1 BIT(4)
291 #define ADMA_DESC_ATTR_ACT2 BIT(5)
292
293 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
294 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
295
296 struct sdhci_adma_desc {
297 u8 attr;
298 u8 reserved;
299 u16 len;
300 u32 addr_lo;
301 #ifdef CONFIG_DMA_ADDR_T_64BIT
302 u32 addr_hi;
303 #endif
304 } __packed;
305
306 struct sdhci_host {
307 const char *name;
308 void *ioaddr;
309 unsigned int quirks;
310 unsigned int host_caps;
311 unsigned int version;
312 unsigned int max_clk; /* Maximum Base Clock frequency */
313 unsigned int clk_mul; /* Clock Multiplier value */
314 unsigned int clock;
315 struct mmc *mmc;
316 const struct sdhci_ops *ops;
317 int index;
318
319 int bus_width;
320 struct gpio_desc pwr_gpio; /* Power GPIO */
321 struct gpio_desc cd_gpio; /* Card Detect GPIO */
322
323 uint voltages;
324
325 struct mmc_config cfg;
326 void *align_buffer;
327 bool force_align_buffer;
328 dma_addr_t start_addr;
329 int flags;
330 #define USE_SDMA (0x1 << 0)
331 #define USE_ADMA (0x1 << 1)
332 #define USE_ADMA64 (0x1 << 2)
333 #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
334 dma_addr_t adma_addr;
335 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
336 struct sdhci_adma_desc *adma_desc_table;
337 #endif
338 };
339
340 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
341
sdhci_writel(struct sdhci_host * host,u32 val,int reg)342 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
343 {
344 if (unlikely(host->ops->write_l))
345 host->ops->write_l(host, val, reg);
346 else
347 writel(val, host->ioaddr + reg);
348 }
349
sdhci_writew(struct sdhci_host * host,u16 val,int reg)350 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
351 {
352 if (unlikely(host->ops->write_w))
353 host->ops->write_w(host, val, reg);
354 else
355 writew(val, host->ioaddr + reg);
356 }
357
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)358 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
359 {
360 if (unlikely(host->ops->write_b))
361 host->ops->write_b(host, val, reg);
362 else
363 writeb(val, host->ioaddr + reg);
364 }
365
sdhci_readl(struct sdhci_host * host,int reg)366 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
367 {
368 if (unlikely(host->ops->read_l))
369 return host->ops->read_l(host, reg);
370 else
371 return readl(host->ioaddr + reg);
372 }
373
sdhci_readw(struct sdhci_host * host,int reg)374 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
375 {
376 if (unlikely(host->ops->read_w))
377 return host->ops->read_w(host, reg);
378 else
379 return readw(host->ioaddr + reg);
380 }
381
sdhci_readb(struct sdhci_host * host,int reg)382 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
383 {
384 if (unlikely(host->ops->read_b))
385 return host->ops->read_b(host, reg);
386 else
387 return readb(host->ioaddr + reg);
388 }
389
390 #else
391
sdhci_writel(struct sdhci_host * host,u32 val,int reg)392 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
393 {
394 writel(val, host->ioaddr + reg);
395 }
396
sdhci_writew(struct sdhci_host * host,u16 val,int reg)397 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
398 {
399 writew(val, host->ioaddr + reg);
400 }
401
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)402 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
403 {
404 writeb(val, host->ioaddr + reg);
405 }
sdhci_readl(struct sdhci_host * host,int reg)406 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
407 {
408 return readl(host->ioaddr + reg);
409 }
410
sdhci_readw(struct sdhci_host * host,int reg)411 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
412 {
413 return readw(host->ioaddr + reg);
414 }
415
sdhci_readb(struct sdhci_host * host,int reg)416 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
417 {
418 return readb(host->ioaddr + reg);
419 }
420 #endif
421
422 #ifdef CONFIG_BLK
423 /**
424 * sdhci_setup_cfg() - Set up the configuration for DWMMC
425 *
426 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
427 *
428 * This should be called from your MMC driver's probe() method once you have
429 * the information required.
430 *
431 * Generally your driver will have a platform data structure which holds both
432 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
433 * For example:
434 *
435 * struct msm_sdhc_plat {
436 * struct mmc_config cfg;
437 * struct mmc mmc;
438 * };
439 *
440 * ...
441 *
442 * Inside U_BOOT_DRIVER():
443 * .plat_auto = sizeof(struct msm_sdhc_plat),
444 *
445 * To access platform data:
446 * struct msm_sdhc_plat *plat = dev_get_plat(dev);
447 *
448 * See msm_sdhci.c for an example.
449 *
450 * @cfg: Configuration structure to fill in (generally &plat->mmc)
451 * @host: SDHCI host structure
452 * @f_max: Maximum supported clock frequency in HZ (0 for default)
453 * @f_min: Minimum supported clock frequency in HZ (0 for default)
454 */
455 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
456 u32 f_max, u32 f_min);
457
458 /**
459 * sdhci_bind() - Set up a new MMC block device
460 *
461 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
462 * It should be called from your driver's bind() method.
463 *
464 * See msm_sdhci.c for an example.
465 *
466 * @dev: Device to set up
467 * @mmc: Pointer to mmc structure (normally &plat->mmc)
468 * @cfg: Empty configuration structure (generally &plat->cfg). This is
469 * normally all zeroes at this point. The only purpose of passing
470 * this in is to set mmc->cfg to it.
471 * @return 0 if OK, -ve if the block device could not be created
472 */
473 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
474 #else
475
476 /**
477 * add_sdhci() - Add a new SDHCI interface
478 *
479 * This is used when you are not using CONFIG_BLK. Convert your driver over!
480 *
481 * @host: SDHCI host structure
482 * @f_max: Maximum supported clock frequency in HZ (0 for default)
483 * @f_min: Minimum supported clock frequency in HZ (0 for default)
484 * @return 0 if OK, -ve on error
485 */
486 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
487 #endif /* !CONFIG_BLK */
488
489 void sdhci_set_uhs_timing(struct sdhci_host *host);
490 #ifdef CONFIG_DM_MMC
491 /* Export the operations to drivers */
492 int sdhci_probe(struct udevice *dev);
493 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
494
495 /**
496 * sdhci_set_control_reg - Set control registers
497 *
498 * This is used set up control registers for voltage level and UHS speed
499 * mode.
500 *
501 * @host: SDHCI host structure
502 */
503 void sdhci_set_control_reg(struct sdhci_host *host);
504 extern const struct dm_mmc_ops sdhci_ops;
505 #else
506 #endif
507
508 struct sdhci_adma_desc *sdhci_adma_init(void);
509 void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
510 struct mmc_data *data, dma_addr_t addr);
511
512 #endif /* __SDHCI_HW_H */
513